From b00030e26731675e523d46ec75a81a1aa19b274c Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 10 May 2021 20:06:06 +0530 Subject: dma: ti: k3-psil: Extend PSIL EP data extension for AM64 Extend PSIL EP data to include AM64 DMA specific information Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-psil.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/dma') diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h index 53c61b4595..1e0fe06c0a 100644 --- a/drivers/dma/ti/k3-psil.h +++ b/drivers/dma/ti/k3-psil.h @@ -50,6 +50,15 @@ enum psil_endpoint_type { * @channel_tpl: Desired throughput level for the channel * @pdma_acc32: ACC32 must be enabled on the PDMA side * @pdma_burst: BURST must be enabled on the PDMA side + * @mapped_channel_id: PKTDMA thread to channel mapping for mapped + * channels. The thread must be serviced by the specified + * channel if mapped_channel_id is >= 0 in case of PKTDMA + * @flow_start: PKTDMA flow range start of mapped channel. Unmapped + * channels use flow_id == chan_id + * @flow_num: PKTDMA flow count of mapped channel. Unmapped + * channels use flow_id == chan_id + * @default_flow_id: PKTDMA default (r)flow index of mapped channel. + * Must be within the flow range of the mapped channel. */ struct psil_endpoint_config { enum psil_endpoint_type ep_type; @@ -63,5 +72,12 @@ struct psil_endpoint_config { /* PDMA properties, valid for PSIL_EP_PDMA_* */ unsigned pdma_acc32:1; unsigned pdma_burst:1; + + /* PKTDMA mapped channel */ + int mapped_channel_id; + /* PKTDMA tflow and rflow ranges for mapped channel */ + u16 flow_start; + u16 flow_num; + u16 default_flow_id; }; #endif /* K3_PSIL_H_ */ -- cgit v1.2.3