From 42e20f52d9a4c76f4740ef6310edaa820028e070 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 10 Aug 2021 06:50:19 -0600 Subject: soc: xilinx: versal: Add soc_xilinx_versal driver soc_xilinx_versal driver allows identification of family & revision of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL. Probe this driver using platdata U_BOOT_DEVICE structure which is defined at mach-versal/cpu.c. Add this config to xilinx_versal_virt_defconfig & xilinx_versal_mini_ospi_defconfig file to select this driver. Signed-off-by: T Karthik Reddy Reviewed-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/soc/Kconfig | 8 +++++ drivers/soc/Makefile | 1 + drivers/soc/soc_xilinx_versal.c | 76 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/soc/soc_xilinx_versal.c (limited to 'drivers/soc') diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 17fb4c4d65..292dc41b6f 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -24,6 +24,14 @@ config SOC_XILINX_ZYNQMP This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +config SOC_XILINX_VERSAL + bool "Enable SoC Device ID driver for Xilinx Versal" + depends on SOC_DEVICE && ARCH_VERSAL + help + Enable this option to select SoC device id driver for Xilinx Versal. + This allows other drivers to verify the SoC familiy & revision using + matching SoC attributes. + source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 9b26573c71..031fa7612f 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o obj-$(CONFIG_SANDBOX) += soc_sandbox.o obj-$(CONFIG_SOC_XILINX_ZYNQMP) += soc_xilinx_zynqmp.o +obj-$(CONFIG_SOC_XILINX_VERSAL) += soc_xilinx_versal.o diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c new file mode 100644 index 0000000000..f8bcd9ab40 --- /dev/null +++ b/drivers/soc/soc_xilinx_versal.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal SOC driver + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include + +/* + * v1 -> 0x10 - ES1 + * v2 -> 0x20 - Production + */ +static const char versal_family[] = "Versal"; + +struct soc_xilinx_versal_priv { + const char *family; + char revision; +}; + +static int soc_xilinx_versal_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_xilinx_versal_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_xilinx_versal_ops = { + .get_family = soc_xilinx_versal_get_family, + .get_revision = soc_xilinx_versal_get_revision, +}; + +static int soc_xilinx_versal_probe(struct udevice *dev) +{ + struct soc_xilinx_versal_priv *priv = dev_get_priv(dev); + u32 ret_payload[4]; + int ret; + + priv->family = versal_family; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret) + return ret; + } else { + ret_payload[2] = readl(VERSAL_PS_PMC_VERSION); + if (!ret_payload[2]) + return -EINVAL; + } + + priv->revision = ret_payload[2] >> VERSAL_PS_VER_SHIFT; + + return 0; +} + +U_BOOT_DRIVER(soc_xilinx_versal) = { + .name = "soc_xilinx_versal", + .id = UCLASS_SOC, + .ops = &soc_xilinx_versal_ops, + .probe = soc_xilinx_versal_probe, + .priv_auto = sizeof(struct soc_xilinx_versal_priv), + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.3