From a890a53ad2cdda973959947619245832203cd7f3 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 10 Aug 2021 06:50:18 -0600 Subject: soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver soc_xilinx_zynqmp driver allows identification of family & revision of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP. Add this config to xilinx_zynqmp_virt_defconfig file. Probe this driver using platdata U_BOOT_DEVICE structure which is specified in mach-zynqmp/cpu.c. Signed-off-by: T Karthik Reddy Reviewed-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/soc/Kconfig | 8 +++++ drivers/soc/Makefile | 1 + drivers/soc/soc_xilinx_zynqmp.c | 78 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/soc/soc_xilinx_zynqmp.c (limited to 'drivers/soc') diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 864d00a885..17fb4c4d65 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -16,6 +16,14 @@ config SOC_DEVICE_TI_K3 This allows Texas Instruments Keystone 3 SoCs to identify specifics about the SoC in use. +config SOC_XILINX_ZYNQMP + bool "Enable SoC Device ID driver for Xilinx ZynqMP" + depends on SOC_DEVICE && ARCH_ZYNQMP + help + Enable this option to select SoC device id driver for Xilinx ZynqMP. + This allows other drivers to verify the SoC familiy & revision + using matching SoC attributes. + source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 9ef20ca506..9b26573c71 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o obj-$(CONFIG_SANDBOX) += soc_sandbox.o +obj-$(CONFIG_SOC_XILINX_ZYNQMP) += soc_xilinx_zynqmp.o diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c new file mode 100644 index 0000000000..7d33ce2163 --- /dev/null +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx ZynqMP SOC driver + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Zynqmp has 4 silicon revisions + * v0 -> 0(XCZU9EG-ES1) + * v1 -> 1(XCZU3EG-ES1, XCZU15EG-ES1) + * v2 -> 2(XCZU7EV-ES1, XCZU9EG-ES2, XCZU19EG-ES1) + * v3 -> 3(Production Level) + */ +static const char zynqmp_family[] = "ZynqMP"; + +struct soc_xilinx_zynqmp_priv { + const char *family; + char revision; +}; + +static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_xilinx_zynqmp_ops = { + .get_family = soc_xilinx_zynqmp_get_family, + .get_revision = soc_xilinx_zynqmp_get_revision, +}; + +static int soc_xilinx_zynqmp_probe(struct udevice *dev) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + u32 ret_payload[4]; + int ret; + + priv->family = zynqmp_family; + + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3 || + !IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) + ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]); + else + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret < 0) + return ret; + + priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK; + + return 0; +} + +U_BOOT_DRIVER(soc_xilinx_zynqmp) = { + .name = "soc_xilinx_zynqmp", + .id = UCLASS_SOC, + .ops = &soc_xilinx_zynqmp_ops, + .probe = soc_xilinx_zynqmp_probe, + .priv_auto = sizeof(struct soc_xilinx_zynqmp_priv), + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.3