From a6903aa7ea98872ff66424051f85cdf0178c86f8 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:08 +0530 Subject: spi: cadence-qspi: Add a small delay before indirect writes Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav Acked-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/spi/cadence_qspi.c') diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index de7628de27..a961193cdc 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -20,6 +20,8 @@ #include #include "cadence_qspi.h" +#define NSEC_PER_SEC 1000000000L + #define CQSPI_STIG_READ 0 #define CQSPI_STIG_WRITE 1 #define CQSPI_READ 2 @@ -208,6 +210,8 @@ static int cadence_spi_probe(struct udevice *bus) priv->qspi_is_init = 1; } + plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz); + return 0; } -- cgit v1.2.3