From 846d1d9c119b9046fa120a76e6d01192fa74ad52 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:22:31 +0200 Subject: mtd: cqspi: Wait for transfer completion Wait for the read/write transfer finish bit get actually cleared, this does not happen immediately on at least SoCFPGA Gen5. Signed-off-by: Marek Vasut Reviewed-by: Jagan Teki Cc: Vignesh R Cc: Pratyush Yadav --- drivers/spi/cadence_qspi_apb.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/spi') diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 429ee335db..2cdf4c9c9f 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); + /* Check indirect done status */ + ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, + CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); + if (ret) { + printf("Indirect read clear completion error (%i)\n", ret); + goto failrd; + } + return 0; failrd: @@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, plat->regbase + CQSPI_REG_INDIRECTWR); + + /* Check indirect done status */ + ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR, + CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0); + if (ret) { + printf("Indirect write clear completion error (%i)\n", ret); + goto failwr; + } + if (bounce_buf) free(bounce_buf); return 0; -- cgit v1.2.3