From 90c98a5ad0ed5de95f2cedf4c755804110377007 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Apr 2019 07:54:54 +0000 Subject: imx8: fuse: add fuse driver Add fuse write for i.MX8 Signed-off-by: Peng Fan --- drivers/misc/imx8/Makefile | 1 + drivers/misc/imx8/fuse.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 drivers/misc/imx8/fuse.c (limited to 'drivers') diff --git a/drivers/misc/imx8/Makefile b/drivers/misc/imx8/Makefile index ee05893cbb..48fdb5b61c 100644 --- a/drivers/misc/imx8/Makefile +++ b/drivers/misc/imx8/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += scu_api.o scu.o +obj-$(CONFIG_CMD_FUSE) += fuse.o diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c new file mode 100644 index 0000000000..29d2256a22 --- /dev/null +++ b/drivers/misc/imx8/fuse.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define FSL_ECC_WORD_START_1 0x10 +#define FSL_ECC_WORD_END_1 0x10F + +#ifdef CONFIG_IMX8QXP +#define FSL_ECC_WORD_START_2 0x220 +#define FSL_ECC_WORD_END_2 0x31F + +#define FSL_QXP_FUSE_GAP_START 0x110 +#define FSL_QXP_FUSE_GAP_END 0x21F +#endif + +#define FSL_SIP_OTP_READ 0xc200000A +#define FSL_SIP_OTP_WRITE 0xc200000B + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + return fuse_sense(bank, word, val); +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + unsigned long ret = 0, value = 0; + + if (bank != 0) { + printf("Invalid bank argument, ONLY bank 0 is supported\n"); + return -EINVAL; + } + + ret = call_imx_sip_ret2(FSL_SIP_OTP_READ, (unsigned long)word, &value, + 0, 0); + *val = (u32)value; + + return ret; +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + if (bank != 0) { + printf("Invalid bank argument, ONLY bank 0 is supported\n"); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_IMX8QXP)) { + if (word >= FSL_QXP_FUSE_GAP_START && + word <= FSL_QXP_FUSE_GAP_END) { + printf("Invalid word argument for this SoC\n"); + return -EINVAL; + } + } + + if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) || + (word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) { + puts("Warning: Words in this index range have ECC protection\n" + "and can only be programmed once per word. Individual bit\n" + "operations will be rejected after the first one.\n" + "\n\n Really program this word? \n"); + + if (!confirm_yesno()) { + puts("Word programming aborted\n"); + return -EPERM; + } + } + + return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word, + (unsigned long)val, 0); +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + printf("Override fuse to i.MX8 in u-boot is forbidden\n"); + return -EPERM; +} -- cgit v1.2.3 From 22988766da6fe200b6947b8181ddbde663643248 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 4 Apr 2019 12:26:52 +0200 Subject: USB: DM: Convert i.MX5 ehci code to driver model This commit converts i.MX5's EHCI USB host driver to driver model (DM_USB). It is a straightforward conversion (to reuse as much code as possible), based on ehci-mx6.c code. Signed-off-by: Lukasz Majewski --- drivers/usb/host/ehci-mx5.c | 103 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 60f1470860..0b32728c57 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include "ehci.h" @@ -223,6 +225,7 @@ __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, mdelay(50); } +#if !CONFIG_IS_ENABLED(DM_USB) static const struct ehci_ops mx5_ehci_ops = { .powerup_fixup = mx5_ehci_powerup_fixup, }; @@ -267,3 +270,103 @@ int ehci_hcd_stop(int index) { return 0; } +#else /* CONFIG_IS_ENABLED(DM_USB) */ +struct ehci_mx5_priv_data { + struct ehci_ctrl ctrl; + struct usb_ehci *ehci; + struct udevice *vbus_supply; + enum usb_init_type init_type; + int portnr; +}; + +static const struct ehci_ops mx5_ehci_ops = { + .powerup_fixup = mx5_ehci_powerup_fixup, +}; + +static int ehci_usb_ofdata_to_platdata(struct udevice *dev) +{ + struct usb_platdata *plat = dev_get_platdata(dev); + const char *mode; + + mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL); + if (mode) { + if (strcmp(mode, "peripheral") == 0) + plat->init_type = USB_INIT_DEVICE; + else if (strcmp(mode, "host") == 0) + plat->init_type = USB_INIT_HOST; + else + return -EINVAL; + } + + return 0; +} + +static int ehci_usb_probe(struct udevice *dev) +{ + struct usb_platdata *plat = dev_get_platdata(dev); + struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev); + struct ehci_mx5_priv_data *priv = dev_get_priv(dev); + enum usb_init_type type = plat->init_type; + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + int ret; + + set_usboh3_clk(); + enable_usboh3_clk(true); + set_usb_phy_clk(); + enable_usb_phy1_clk(true); + enable_usb_phy2_clk(true); + mdelay(1); + + priv->ehci = ehci; + priv->portnr = dev->seq; + priv->init_type = type; + + ret = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); + if (ret) + debug("%s: No vbus supply\n", dev->name); + + if (!ret && priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); + if (ret) { + puts("Error enabling VBUS supply\n"); + return ret; + } + } + + hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); + setbits_le32(&ehci->usbmode, CM_HOST); + + __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + + mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS); + mdelay(10); + + return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0, + priv->init_type); +} + +static const struct udevice_id mx5_usb_ids[] = { + { .compatible = "fsl,imx53-usb" }, + { } +}; + +U_BOOT_DRIVER(usb_mx5) = { + .name = "ehci_mx5", + .id = UCLASS_USB, + .of_match = mx5_usb_ids, + .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, + .probe = ehci_usb_probe, + .remove = ehci_deregister, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif /* !CONFIG_IS_ENABLED(DM_USB) */ -- cgit v1.2.3 From 400b972a7eb7756dcf111990d6d16187c30ae9db Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 4 Apr 2019 12:26:55 +0200 Subject: Convert CONFIG_USB_EHCI_MX5 to Kconfig This converts the following to Kconfig: CONFIG_USB_EHCI_MX5 Signed-off-by: Lukasz Majewski --- configs/kp_imx53_defconfig | 1 + configs/m53menlo_defconfig | 1 + configs/mx51evk_defconfig | 1 + configs/mx53loco_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/usbarmory_defconfig | 1 + drivers/usb/host/Kconfig | 7 +++++++ include/configs/kp_imx53.h | 1 - include/configs/m53menlo.h | 1 - include/configs/mx51evk.h | 1 - include/configs/mx53cx9020.h | 1 - include/configs/mx53loco.h | 1 - include/configs/mx53ppd.h | 1 - include/configs/usbarmory.h | 1 - scripts/config_whitelist.txt | 1 - 15 files changed, 13 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index 45227c26d2..225be66019 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -45,4 +45,5 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=2 CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index e830b2c92e..e10cb8ed8d 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -58,6 +58,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_RTC_M41T62=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index dc0b3b3f77..78aa89d651 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -26,6 +26,7 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 776fc8bab4..caf04ad894 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -26,6 +26,7 @@ CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y CONFIG_MII=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 2a6183b77b..2379ab8c66 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MII=y CONFIG_RTC_S35392A=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index b1f872405b..46f9996e18 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -15,4 +15,5 @@ CONFIG_CMD_USB=y CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_USB=y +CONFIG_USB_EHCI_MX5=y CONFIG_OF_LIBFDT=y diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0fbc115801..1c2212f547 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -132,6 +132,13 @@ config USB_EHCI_MARVELL ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs. +config USB_EHCI_MX5 + bool "Support for i.MX5 on-chip EHCI USB controller" + depends on ARCH_MX5 + default n + help + Enables support for the on-chip EHCI controller on i.MX5 SoCs. + config USB_EHCI_MX6 bool "Support for i.MX6 on-chip EHCI USB controller" depends on ARCH_MX6 diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index d09608df35..a252e9003d 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 84d061339e..82842d8426 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -118,7 +118,6 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 9bf9773c69..f5fd01de22 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -61,7 +61,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 1e3ea88b77..9bf5d9169b 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -41,7 +41,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 2d18f05423..4f179081a8 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -38,7 +38,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index f002324fdd..2d6715cba2 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -37,7 +37,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_MCS7830 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 270f325a55..128f02db66 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_FSL_ESDHC_NUM 1 /* USB */ -#define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 421362d953..d9caa2b8d4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4504,7 +4504,6 @@ CONFIG_USB_EHCI_BASE_LIST CONFIG_USB_EHCI_EXYNOS CONFIG_USB_EHCI_FARADAY CONFIG_USB_EHCI_KIRKWOOD -CONFIG_USB_EHCI_MX5 CONFIG_USB_EHCI_MXC CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_SPEAR -- cgit v1.2.3 From a413c17e41a36e1937dd89d0cffa36e96c3b3c8c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 Mar 2019 02:32:13 +0000 Subject: pinctrl: imx8: add i.MX8QM compatible Add i.MX8QM compatible Signed-off-by: Peng Fan --- drivers/pinctrl/nxp/pinctrl-imx8.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c index 0738da0ebe..c1b0ca438a 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -25,6 +25,7 @@ static int imx8_pinctrl_probe(struct udevice *dev) static const struct udevice_id imx8_pinctrl_match[] = { { .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info }, + { .compatible = "fsl,imx8qm-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info }, { /* sentinel */ } }; -- cgit v1.2.3 From 98c63a78408e87fcbf0ea200c7a2306a76da9021 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 Mar 2019 02:32:33 +0000 Subject: clk: imx8: split code into common and soc specific part To make it easy to add new clk driver for i.MX8, split the code into common part and SoC specific part. Make the get/set/enable non static and introduce a num_clks for soc_clk_dump, because the arrays are moved to clk-imx8qxp.c. Signed-off-by: Peng Fan --- drivers/clk/imx/Makefile | 4 + drivers/clk/imx/clk-imx8.c | 297 ++-------------------------------------- drivers/clk/imx/clk-imx8.h | 19 +++ drivers/clk/imx/clk-imx8qxp.c | 311 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 342 insertions(+), 289 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8.h create mode 100644 drivers/clk/imx/clk-imx8qxp.c (limited to 'drivers') diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 5505ae52e2..d07d91b88f 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -3,3 +3,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CLK_IMX8) += clk-imx8.o + +ifdef CONFIG_CLK_IMX8 +obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o +endif diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index d03fcc2fdd..c69a9ed867 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -13,302 +13,21 @@ #include #include -struct imx8_clks { - ulong id; - const char *name; -}; - -#if CONFIG_IS_ENABLED(CMD_CLK) -static struct imx8_clks imx8_clk_names[] = { - { IMX8QXP_A35_DIV, "A35_DIV" }, - { IMX8QXP_I2C0_CLK, "I2C0" }, - { IMX8QXP_I2C1_CLK, "I2C1" }, - { IMX8QXP_I2C2_CLK, "I2C2" }, - { IMX8QXP_I2C3_CLK, "I2C3" }, - { IMX8QXP_UART0_CLK, "UART0" }, - { IMX8QXP_UART1_CLK, "UART1" }, - { IMX8QXP_UART2_CLK, "UART2" }, - { IMX8QXP_UART3_CLK, "UART3" }, - { IMX8QXP_SDHC0_CLK, "SDHC0" }, - { IMX8QXP_SDHC1_CLK, "SDHC1" }, - { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" }, - { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" }, - { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" }, - { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" }, - { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" }, - { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" }, - { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" }, - { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" }, -}; -#endif +#include "clk-imx8.h" -static ulong imx8_clk_get_rate(struct clk *clk) +__weak ulong imx8_clk_get_rate(struct clk *clk) { - sc_pm_clk_t pm_clk; - ulong rate; - u16 resource; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - switch (clk->id) { - case IMX8QXP_A35_DIV: - resource = SC_R_A35; - pm_clk = SC_PM_CLK_CPU; - break; - case IMX8QXP_I2C0_CLK: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C1_CLK: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C2_CLK: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C3_CLK: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC0_IPG_CLK: - case IMX8QXP_SDHC0_CLK: - case IMX8QXP_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC1_IPG_CLK: - case IMX8QXP_SDHC1_CLK: - case IMX8QXP_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART0_IPG_CLK: - case IMX8QXP_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET0_IPG_CLK: - case IMX8QXP_ENET0_AHB_CLK: - case IMX8QXP_ENET0_REF_DIV: - case IMX8QXP_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET1_IPG_CLK: - case IMX8QXP_ENET1_AHB_CLK: - case IMX8QXP_ENET1_REF_DIV: - case IMX8QXP_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QXP_UART0_IPG_CLK || - clk->id >= IMX8QXP_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - }; - - ret = sc_pm_get_clock_rate(-1, resource, pm_clk, - (sc_pm_clock_rate_t *)&rate); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } - - return rate; + return 0; } -static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) +__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) { - sc_pm_clk_t pm_clk; - u32 new_rate = rate; - u16 resource; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - switch (clk->id) { - case IMX8QXP_I2C0_CLK: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C1_CLK: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C2_CLK: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C3_CLK: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC0_IPG_CLK: - case IMX8QXP_SDHC0_CLK: - case IMX8QXP_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC1_SEL: - case IMX8QXP_SDHC0_SEL: - return 0; - case IMX8QXP_SDHC1_IPG_CLK: - case IMX8QXP_SDHC1_CLK: - case IMX8QXP_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET0_IPG_CLK: - case IMX8QXP_ENET0_AHB_CLK: - case IMX8QXP_ENET0_REF_DIV: - case IMX8QXP_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET1_IPG_CLK: - case IMX8QXP_ENET1_AHB_CLK: - case IMX8QXP_ENET1_REF_DIV: - case IMX8QXP_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QXP_UART0_IPG_CLK || - clk->id >= IMX8QXP_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - }; - - ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } - - return new_rate; + return 0; } -static int __imx8_clk_enable(struct clk *clk, bool enable) +__weak int __imx8_clk_enable(struct clk *clk, bool enable) { - sc_pm_clk_t pm_clk; - u16 resource; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - switch (clk->id) { - case IMX8QXP_I2C0_CLK: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C1_CLK: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C2_CLK: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C3_CLK: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC0_IPG_CLK: - case IMX8QXP_SDHC0_CLK: - case IMX8QXP_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC1_IPG_CLK: - case IMX8QXP_SDHC1_CLK: - case IMX8QXP_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET0_IPG_CLK: - case IMX8QXP_ENET0_AHB_CLK: - case IMX8QXP_ENET0_REF_DIV: - case IMX8QXP_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET1_IPG_CLK: - case IMX8QXP_ENET1_AHB_CLK: - case IMX8QXP_ENET1_REF_DIV: - case IMX8QXP_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QXP_UART0_IPG_CLK || - clk->id >= IMX8QXP_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - } - - ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } - - return 0; + return -ENOTSUPP; } static int imx8_clk_disable(struct clk *clk) @@ -336,7 +55,7 @@ int soc_clk_dump(void) printf("Clk\t\tHz\n"); - for (i = 0; i < ARRAY_SIZE(imx8_clk_names); i++) { + for (i = 0; i < num_clks; i++) { clk.id = imx8_clk_names[i].id; ret = clk_request(dev, &clk); if (ret < 0) { diff --git a/drivers/clk/imx/clk-imx8.h b/drivers/clk/imx/clk-imx8.h new file mode 100644 index 0000000000..68ad6755e8 --- /dev/null +++ b/drivers/clk/imx/clk-imx8.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * Peng Fan + */ + +struct imx8_clks { + ulong id; + const char *name; +}; + +#if CONFIG_IS_ENABLED(CMD_CLK) +extern struct imx8_clks imx8_clk_names[]; +extern int num_clks; +#endif + +ulong imx8_clk_get_rate(struct clk *clk); +ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate); +int __imx8_clk_enable(struct clk *clk, bool enable); diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c new file mode 100644 index 0000000000..1fca36ac91 --- /dev/null +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP + * Peng Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-imx8.h" + +#if CONFIG_IS_ENABLED(CMD_CLK) +struct imx8_clks imx8_clk_names[] = { + { IMX8QXP_A35_DIV, "A35_DIV" }, + { IMX8QXP_I2C0_CLK, "I2C0" }, + { IMX8QXP_I2C1_CLK, "I2C1" }, + { IMX8QXP_I2C2_CLK, "I2C2" }, + { IMX8QXP_I2C3_CLK, "I2C3" }, + { IMX8QXP_UART0_CLK, "UART0" }, + { IMX8QXP_UART1_CLK, "UART1" }, + { IMX8QXP_UART2_CLK, "UART2" }, + { IMX8QXP_UART3_CLK, "UART3" }, + { IMX8QXP_SDHC0_CLK, "SDHC0" }, + { IMX8QXP_SDHC1_CLK, "SDHC1" }, + { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" }, + { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" }, + { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" }, + { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" }, + { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" }, + { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" }, + { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" }, + { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" }, +}; + +int num_clks = ARRAY_SIZE(imx8_clk_names); +#endif + +ulong imx8_clk_get_rate(struct clk *clk) +{ + sc_pm_clk_t pm_clk; + ulong rate; + u16 resource; + int ret; + + debug("%s(#%lu)\n", __func__, clk->id); + + switch (clk->id) { + case IMX8QXP_A35_DIV: + resource = SC_R_A35; + pm_clk = SC_PM_CLK_CPU; + break; + case IMX8QXP_I2C0_CLK: + resource = SC_R_I2C_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C1_CLK: + resource = SC_R_I2C_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C2_CLK: + resource = SC_R_I2C_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C3_CLK: + resource = SC_R_I2C_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC0_IPG_CLK: + case IMX8QXP_SDHC0_CLK: + case IMX8QXP_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC1_IPG_CLK: + case IMX8QXP_SDHC1_CLK: + case IMX8QXP_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART0_IPG_CLK: + case IMX8QXP_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_ENET0_IPG_CLK: + case IMX8QXP_ENET0_AHB_CLK: + case IMX8QXP_ENET0_REF_DIV: + case IMX8QXP_ENET0_PTP_CLK: + resource = SC_R_ENET_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_ENET1_IPG_CLK: + case IMX8QXP_ENET1_AHB_CLK: + case IMX8QXP_ENET1_REF_DIV: + case IMX8QXP_ENET1_PTP_CLK: + resource = SC_R_ENET_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + if (clk->id < IMX8QXP_UART0_IPG_CLK || + clk->id >= IMX8QXP_CLK_END) { + printf("%s(Invalid clk ID #%lu)\n", + __func__, clk->id); + return -EINVAL; + } + return -ENOTSUPP; + }; + + ret = sc_pm_get_clock_rate(-1, resource, pm_clk, + (sc_pm_clock_rate_t *)&rate); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return rate; +} + +ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) +{ + sc_pm_clk_t pm_clk; + u32 new_rate = rate; + u16 resource; + int ret; + + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); + + switch (clk->id) { + case IMX8QXP_I2C0_CLK: + resource = SC_R_I2C_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C1_CLK: + resource = SC_R_I2C_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C2_CLK: + resource = SC_R_I2C_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C3_CLK: + resource = SC_R_I2C_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC0_IPG_CLK: + case IMX8QXP_SDHC0_CLK: + case IMX8QXP_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC1_SEL: + case IMX8QXP_SDHC0_SEL: + return 0; + case IMX8QXP_SDHC1_IPG_CLK: + case IMX8QXP_SDHC1_CLK: + case IMX8QXP_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_ENET0_IPG_CLK: + case IMX8QXP_ENET0_AHB_CLK: + case IMX8QXP_ENET0_REF_DIV: + case IMX8QXP_ENET0_PTP_CLK: + resource = SC_R_ENET_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_ENET1_IPG_CLK: + case IMX8QXP_ENET1_AHB_CLK: + case IMX8QXP_ENET1_REF_DIV: + case IMX8QXP_ENET1_PTP_CLK: + resource = SC_R_ENET_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + if (clk->id < IMX8QXP_UART0_IPG_CLK || + clk->id >= IMX8QXP_CLK_END) { + printf("%s(Invalid clk ID #%lu)\n", + __func__, clk->id); + return -EINVAL; + } + return -ENOTSUPP; + }; + + ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return new_rate; +} + +int __imx8_clk_enable(struct clk *clk, bool enable) +{ + sc_pm_clk_t pm_clk; + u16 resource; + int ret; + + debug("%s(#%lu)\n", __func__, clk->id); + + switch (clk->id) { + case IMX8QXP_I2C0_CLK: + resource = SC_R_I2C_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C1_CLK: + resource = SC_R_I2C_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C2_CLK: + resource = SC_R_I2C_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_I2C3_CLK: + resource = SC_R_I2C_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC0_IPG_CLK: + case IMX8QXP_SDHC0_CLK: + case IMX8QXP_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_SDHC1_IPG_CLK: + case IMX8QXP_SDHC1_CLK: + case IMX8QXP_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_ENET0_IPG_CLK: + case IMX8QXP_ENET0_AHB_CLK: + case IMX8QXP_ENET0_REF_DIV: + case IMX8QXP_ENET0_PTP_CLK: + resource = SC_R_ENET_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QXP_ENET1_IPG_CLK: + case IMX8QXP_ENET1_AHB_CLK: + case IMX8QXP_ENET1_REF_DIV: + case IMX8QXP_ENET1_PTP_CLK: + resource = SC_R_ENET_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + if (clk->id < IMX8QXP_UART0_IPG_CLK || + clk->id >= IMX8QXP_CLK_END) { + printf("%s(Invalid clk ID #%lu)\n", + __func__, clk->id); + return -EINVAL; + } + return -ENOTSUPP; + } + + ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return 0; +} -- cgit v1.2.3 From e45efe90cd3b1e02994c3cc9c465151e9bef3864 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 Mar 2019 02:32:35 +0000 Subject: clk: imx8: add i.MX8QM clk driver Add i.MX8QM clk driver, SDHC/FEC/UART/I2C supported. Signed-off-by: Peng Fan --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx8.c | 1 + drivers/clk/imx/clk-imx8qm.c | 307 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 309 insertions(+) create mode 100644 drivers/clk/imx/clk-imx8qm.c (limited to 'drivers') diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index d07d91b88f..eb379c188a 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_CLK_IMX8) += clk-imx8.o ifdef CONFIG_CLK_IMX8 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o +obj-$(CONFIG_IMX8QM) += clk-imx8qm.o endif diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index c69a9ed867..a755e26501 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -101,6 +101,7 @@ static int imx8_clk_probe(struct udevice *dev) static const struct udevice_id imx8_clk_ids[] = { { .compatible = "fsl,imx8qxp-clk" }, + { .compatible = "fsl,imx8qm-clk" }, { }, }; diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c new file mode 100644 index 0000000000..6b5561e178 --- /dev/null +++ b/drivers/clk/imx/clk-imx8qm.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP + * Peng Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-imx8.h" + +#if CONFIG_IS_ENABLED(CMD_CLK) +struct imx8_clks imx8_clk_names[] = { + { IMX8QM_A53_DIV, "A53_DIV" }, + { IMX8QM_UART0_CLK, "UART0" }, + { IMX8QM_UART1_CLK, "UART1" }, + { IMX8QM_UART2_CLK, "UART2" }, + { IMX8QM_UART3_CLK, "UART3" }, + { IMX8QM_SDHC0_CLK, "SDHC0" }, + { IMX8QM_SDHC1_CLK, "SDHC1" }, + { IMX8QM_SDHC2_CLK, "SDHC2" }, + { IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" }, + { IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" }, + { IMX8QM_ENET0_REF_DIV, "ENET0_REF" }, + { IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" }, + { IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" }, + { IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" }, + { IMX8QM_ENET1_REF_DIV, "ENET1_REF" }, + { IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" }, +}; + +int num_clks = ARRAY_SIZE(imx8_clk_names); +#endif + +ulong imx8_clk_get_rate(struct clk *clk) +{ + sc_pm_clk_t pm_clk; + ulong rate; + u16 resource; + int ret; + + debug("%s(#%lu)\n", __func__, clk->id); + + switch (clk->id) { + case IMX8QM_A53_DIV: + resource = SC_R_A53; + pm_clk = SC_PM_CLK_CPU; + break; + case IMX8QM_I2C0_CLK: + resource = SC_R_I2C_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C1_CLK: + resource = SC_R_I2C_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C2_CLK: + resource = SC_R_I2C_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C3_CLK: + resource = SC_R_I2C_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_SDHC0_IPG_CLK: + case IMX8QM_SDHC0_CLK: + case IMX8QM_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_SDHC1_IPG_CLK: + case IMX8QM_SDHC1_CLK: + case IMX8QM_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART0_IPG_CLK: + case IMX8QM_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_ENET0_IPG_CLK: + case IMX8QM_ENET0_AHB_CLK: + case IMX8QM_ENET0_REF_DIV: + case IMX8QM_ENET0_PTP_CLK: + resource = SC_R_ENET_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_ENET1_IPG_CLK: + case IMX8QM_ENET1_AHB_CLK: + case IMX8QM_ENET1_REF_DIV: + case IMX8QM_ENET1_PTP_CLK: + resource = SC_R_ENET_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + if (clk->id < IMX8QM_UART0_IPG_CLK || + clk->id >= IMX8QM_CLK_END) { + printf("%s(Invalid clk ID #%lu)\n", + __func__, clk->id); + return -EINVAL; + } + return -ENOTSUPP; + }; + + ret = sc_pm_get_clock_rate(-1, resource, pm_clk, + (sc_pm_clock_rate_t *)&rate); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return rate; +} + +ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) +{ + sc_pm_clk_t pm_clk; + u32 new_rate = rate; + u16 resource; + int ret; + + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); + + switch (clk->id) { + case IMX8QM_I2C0_CLK: + resource = SC_R_I2C_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C1_CLK: + resource = SC_R_I2C_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C2_CLK: + resource = SC_R_I2C_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C3_CLK: + resource = SC_R_I2C_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_SDHC0_IPG_CLK: + case IMX8QM_SDHC0_CLK: + case IMX8QM_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_SDHC1_IPG_CLK: + case IMX8QM_SDHC1_CLK: + case IMX8QM_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_ENET0_IPG_CLK: + case IMX8QM_ENET0_AHB_CLK: + case IMX8QM_ENET0_REF_DIV: + case IMX8QM_ENET0_PTP_CLK: + case IMX8QM_ENET0_ROOT_DIV: + resource = SC_R_ENET_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_ENET1_IPG_CLK: + case IMX8QM_ENET1_AHB_CLK: + case IMX8QM_ENET1_REF_DIV: + case IMX8QM_ENET1_PTP_CLK: + case IMX8QM_ENET1_ROOT_DIV: + resource = SC_R_ENET_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + if (clk->id < IMX8QM_UART0_IPG_CLK || + clk->id >= IMX8QM_CLK_END) { + printf("%s(Invalid clk ID #%lu)\n", + __func__, clk->id); + return -EINVAL; + } + return -ENOTSUPP; + }; + + ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return new_rate; +} + +int __imx8_clk_enable(struct clk *clk, bool enable) +{ + sc_pm_clk_t pm_clk; + u16 resource; + int ret; + + debug("%s(#%lu)\n", __func__, clk->id); + + switch (clk->id) { + case IMX8QM_I2C0_CLK: + resource = SC_R_I2C_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C1_CLK: + resource = SC_R_I2C_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C2_CLK: + resource = SC_R_I2C_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_I2C3_CLK: + resource = SC_R_I2C_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART0_CLK: + resource = SC_R_UART_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART1_CLK: + resource = SC_R_UART_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART2_CLK: + resource = SC_R_UART_2; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_UART3_CLK: + resource = SC_R_UART_3; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_SDHC0_IPG_CLK: + case IMX8QM_SDHC0_CLK: + case IMX8QM_SDHC0_DIV: + resource = SC_R_SDHC_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_SDHC1_IPG_CLK: + case IMX8QM_SDHC1_CLK: + case IMX8QM_SDHC1_DIV: + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_ENET0_IPG_CLK: + case IMX8QM_ENET0_AHB_CLK: + case IMX8QM_ENET0_REF_DIV: + case IMX8QM_ENET0_PTP_CLK: + resource = SC_R_ENET_0; + pm_clk = SC_PM_CLK_PER; + break; + case IMX8QM_ENET1_IPG_CLK: + case IMX8QM_ENET1_AHB_CLK: + case IMX8QM_ENET1_REF_DIV: + case IMX8QM_ENET1_PTP_CLK: + resource = SC_R_ENET_1; + pm_clk = SC_PM_CLK_PER; + break; + default: + if (clk->id < IMX8QM_UART0_IPG_CLK || + clk->id >= IMX8QM_CLK_END) { + printf("%s(Invalid clk ID #%lu)\n", + __func__, clk->id); + return -EINVAL; + } + return -ENOTSUPP; + } + + ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return 0; +} -- cgit v1.2.3 From 894e02b7b0276af80f52d47cbc6565275262c098 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 Mar 2019 02:32:45 +0000 Subject: misc: imx8: scu: add i.MX8QM support According to IMX8QXP/8QM config option, choose the clk/iomuxc compatible. Signed-off-by: Peng Fan --- drivers/misc/imx8/scu.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 1b9c49c99c..9ec00457b8 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -219,11 +219,21 @@ static int imx8_scu_bind(struct udevice *dev) int ret; struct udevice *child; int node; + char *clk_compatible, *iomuxc_compatible; + + if (IS_ENABLED(CONFIG_IMX8QXP)) { + clk_compatible = "fsl,imx8qxp-clk"; + iomuxc_compatible = "fsl,imx8qxp-iomuxc"; + } else if (IS_ENABLED(CONFIG_IMX8QM)) { + clk_compatible = "fsl,imx8qm-clk"; + iomuxc_compatible = "fsl,imx8qm-iomuxc"; + } else { + return -EINVAL; + } debug("%s(dev=%p)\n", __func__, dev); - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, - "fsl,imx8qxp-clk"); + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, clk_compatible); if (node < 0) panic("No clk node found\n"); @@ -234,7 +244,7 @@ static int imx8_scu_bind(struct udevice *dev) plat->clk = child; node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, - "fsl,imx8qxp-iomuxc"); + iomuxc_compatible); if (node < 0) panic("No iomuxc node found\n"); -- cgit v1.2.3 From 112ad600587655d17a95ecf1d9a10358528106ac Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 17 Apr 2019 09:41:20 +0000 Subject: mxc_ocotp: Update redundancy banks for mx7ulp B0 On mx7ulp B0, beside bank 0 and 1, the fuse bank 9, 10, 28 are changed to Redundancy mode not ECC, so they can support to program different bits of a word in multiple times. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/misc/mxc_ocotp.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index f84fe88db1..33ea31135c 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -354,13 +354,17 @@ static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, /* Only bank 0 and 1 are redundancy mode, others are ECC mode */ if (bank != 0 && bank != 1) { - ret = fuse_sense(bank, word, &val); - if (ret) - return ret; - - if (val != 0) { - printf("mxc_ocotp: The word has been programmed, no more write\n"); - return -EPERM; + if ((soc_rev() < CHIP_REV_2_0) || + ((soc_rev() >= CHIP_REV_2_0) && + bank != 9 && bank != 10 && bank != 28)) { + ret = fuse_sense(bank, word, &val); + if (ret) + return ret; + + if (val != 0) { + printf("mxc_ocotp: The word has been programmed, no more write\n"); + return -EPERM; + } } } #endif -- cgit v1.2.3 From b3cf86c86bf00d7d3ee9bc7ecb0819105b641c89 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 17 Apr 2019 09:41:23 +0000 Subject: mxc_ocotp: Disable fuse sense for imx8mq B1 On iMX8MQ Rev B1, reading from fuse box is not allowed. The OCOTP_READ_FUSE_DATA register is tied to magic number 0xff0055aa for chip rev. So u-boot has to disable the fuse sense function for it. Signed-off-by: Ye Li Tested-by: Anson Huang Signed-off-by: Peng Fan --- drivers/misc/mxc_ocotp.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 33ea31135c..1b945e9727 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -321,6 +321,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val) struct ocotp_regs *regs; int ret; + if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) { + printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__); + return -EPERM; + } + ret = prepare_read(®s, bank, word, val, __func__); if (ret) return ret; -- cgit v1.2.3 From 5e479ccdf104c131537cebf6345729f30864ac8f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Apr 2019 10:41:28 +0000 Subject: ddr: imx8m: hide i.MX8M DDR options from device driver entry Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig index 71f466f5ec..a83b0f43d7 100644 --- a/drivers/ddr/imx/imx8m/Kconfig +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -1,3 +1,6 @@ +menu "i.MX8M DDR controllers" + depends on ARCH_IMX8M + config IMX8M_DRAM bool "imx8m dram" @@ -20,3 +23,4 @@ config SAVED_DRAM_TIMING_BASE info into memory for low power use. OCRAM_S is used for this purpose on i.MX8MM. default 0x180000 +endmenu -- cgit v1.2.3