From 2ddf554b8648d892efc5733e7486cec5e93dc269 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sat, 31 Jul 2021 14:22:53 +0200 Subject: arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- include/configs/db-88f6720.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 410a40af3e..18f4707e6b 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -15,7 +15,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ /* I2C */ #define CONFIG_SYS_I2C_LEGACY -- cgit v1.2.3