From 8b41464547330a39cc7e0ef87a5dd8f34db324e1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 11 Apr 2018 17:07:45 +0200 Subject: clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI output P can be used as 48MHz clock source for USB and SDMMC. Signed-off-by: Patrice Chotard Tested By: Bruno Herrera --- include/stm32_rcc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/stm32_rcc.h') diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index 748c2ebd0c..71da3c1a87 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h @@ -40,7 +40,8 @@ struct stm32_clk_info { }; enum soc_family { - STM32F4, + STM32F42X, + STM32F469, STM32F7, }; -- cgit v1.2.3