From 26e054c943a7348904a8b432fc9a85185b0861c7 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 5 Aug 2019 15:54:59 +0530 Subject: arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/xilinx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/xilinx.h') diff --git a/include/xilinx.h b/include/xilinx.h index af40befa52..ab4537becf 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -21,6 +21,7 @@ typedef enum { /* typedef xilinx_iface */ slave_selectmap, /* slave SelectMap (virtex2) */ devcfg, /* devcfg interface (zynq) */ csu_dma, /* csu_dma interface (zynqmp) */ + cfi, /* CFI interface(versal) */ max_xilinx_iface_type /* insert all new types before this */ } xilinx_iface; /* end, typedef xilinx_iface */ @@ -32,6 +33,7 @@ typedef enum { /* typedef xilinx_family */ xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ xilinx_zynqmp, /* ZynqMP Family */ + xilinx_versal, /* Versal Family */ max_xilinx_type /* insert all new types before this */ } xilinx_family; /* end, typedef xilinx_family */ -- cgit v1.2.3