From 7635defaf2c65755a19e6faa08d604421ad2a06f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 23 Jun 2020 08:20:07 -0400 Subject: configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini --- scripts/config_whitelist.txt | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'scripts') diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f6bf6f2474..916768f361 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1416,8 +1416,6 @@ CONFIG_RESET_TO_RETRY CONFIG_RESET_VECTOR_ADDRESS CONFIG_RESTORE_FLASH CONFIG_RES_BLOCK_SIZE -CONFIG_REV1 -CONFIG_REV3 CONFIG_REVISION_TAG CONFIG_RFSPART CONFIG_RIO @@ -2226,10 +2224,6 @@ CONFIG_SYS_DSPI_CTAR0 CONFIG_SYS_DSPI_CTAR1 CONFIG_SYS_DSPI_CTAR2 CONFIG_SYS_DSPI_CTAR3 -CONFIG_SYS_DSPI_CTAR4 -CONFIG_SYS_DSPI_CTAR5 -CONFIG_SYS_DSPI_CTAR6 -CONFIG_SYS_DSPI_CTAR7 CONFIG_SYS_DV_NOR_BOOT_CFG CONFIG_SYS_EBI_CFGR_VAL CONFIG_SYS_EBI_CSA_VAL @@ -3789,14 +3783,6 @@ CONFIG_SYS_SPCR_OPT CONFIG_SYS_SPCR_TSEC1EP CONFIG_SYS_SPCR_TSEC2EP CONFIG_SYS_SPD_BUS_NUM -CONFIG_SYS_SPI0 -CONFIG_SYS_SPI0_NUM_CS -CONFIG_SYS_SPI1 -CONFIG_SYS_SPI1_BASE -CONFIG_SYS_SPI1_NUM_CS -CONFIG_SYS_SPI2 -CONFIG_SYS_SPI2_BASE -CONFIG_SYS_SPI2_NUM_CS CONFIG_SYS_SPI_ARGS_OFFS CONFIG_SYS_SPI_ARGS_SIZE CONFIG_SYS_SPI_BASE -- cgit v1.2.3 From f44bd3bcfd91cd7b1be709c9cfb0824e6a71b9b0 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 18 May 2020 01:11:00 -0600 Subject: spi: zynq_[q]spi: Convert config's to macro's Remove below config options and convert them to macros. They have never been configured to different values than default one. And also it makes sense to reduce the config_whitelist. CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_XILINX_SPI_IDLE_VAL Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/spi/xilinx_spi.c | 6 ++---- drivers/spi/zynq_qspi.c | 6 ++---- drivers/spi/zynq_spi.c | 6 ++---- scripts/config_whitelist.txt | 3 --- 4 files changed, 6 insertions(+), 15 deletions(-) (limited to 'scripts') diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 05768eef72..348630faf3 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -76,9 +76,7 @@ SPICR_SPE) #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) -#ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) -#endif +#define XILINX_SPI_IDLE_VAL GENMASK(7, 0) #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */ @@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp, while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) && i < priv->fifo_depth) { - d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; + d = txp ? *txp++ : XILINX_SPI_IDLE_VAL; debug("spi_xfer: tx:%x ", d); /* write out and wait for processing (receive data) */ writel(d & SPIDTR_8BIT_MASK, ®s->spidtr); diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index db473da6ea..3f39ef05f2 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -47,9 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */ #define ZYNQ_QSPI_FIFO_DEPTH 63 -#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT -#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ -#endif +#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */ /* zynq qspi register set */ struct zynq_qspi_regs { @@ -350,7 +348,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) do { status = readl(®s->isr); } while ((status == 0) && - (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT)); + (get_timer(timeout) < ZYNQ_QSPI_WAIT)); if (status == 0) { printf("zynq_qspi_irq_poll: Timeout!\n"); diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 3e66b34ebb..78ffd3e2fe 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -36,9 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ #define ZYNQ_SPI_FIFO_DEPTH 128 -#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT -#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ -#endif +#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */ /* zynq spi register set */ struct zynq_spi_regs { @@ -251,7 +249,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, ts = get_timer(0); status = readl(®s->isr); while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { - if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { + if (get_timer(ts) > ZYNQ_SPI_WAIT) { printf("spi_xfer: Timeout! TX FIFO not full\n"); return -1; } diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 916768f361..b023806efc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3984,8 +3984,6 @@ CONFIG_SYS_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB3_ADDR CONFIG_SYS_XIMG_LEN -CONFIG_SYS_ZYNQ_QSPI_WAIT -CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL CONFIG_TAM3517_SETTINGS CONFIG_TCA642X @@ -4211,7 +4209,6 @@ CONFIG_X86_MRC_ADDR CONFIG_X86_REFCODE_ADDR CONFIG_X86_REFCODE_RUN_ADDR CONFIG_XGI_XG22_BASE -CONFIG_XILINX_SPI_IDLE_VAL CONFIG_XSENGINE CONFIG_XTFPGA CONFIG_YAFFSFS_PROVIDE_VALUES -- cgit v1.2.3