1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
|
// SPDX-License-Identifier: GPL-2.0
/*
* DTS File for HiSilicon Hi3798mv200 SoC.
*
* Released under the GPLv2 only.
*/
#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "hisilicon,hi3798mv200";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x100>; /* GICC */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
/* Initialization is done in boot loader */
usb2_phy1: hsusb1_phy {
compatible = "usb-nop-xceiv";
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
clock-names = "main";
#phy-cells = <0>;
};
soc: soc@f0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd";
reg = <0x8a22000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
sysctrl: system-controller@8000000 {
compatible = "hisilicon,hi3798mv200-sysctrl", "syscon";
reg = <0x8000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
perictrl: peripheral-controller@8a20000 {
compatible = "hisilicon,hi3798mv200-perictrl", "syscon",
"simple-mfd";
reg = <0x8a20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x8a20000 0x1000>;
combphy0: phy@850 {
compatible = "hisilicon,hi3798mv200-combphy";
reg = <0x850 0x8>;
#phy-cells = <1>;
clocks = <&crg HISTB_COMBPHY0_CLK>;
resets = <&crg 0x188 4>;
assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
assigned-clock-rates = <100000000>;
hisilicon,fixed-mode = <PHY_TYPE_USB3>;
};
};
pmx0: pinconf@8a21000 {
compatible = "pinconf-single";
reg = <0x8a21000 0x180>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
};
uart0: serial@8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
sd0: mmc@9820000 {
compatible = "snps,dw-mshc";
reg = <0x9820000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_SDIO0_CIU_CLK>,
<&crg HISTB_SDIO0_BIU_CLK>;
clock-names = "ciu", "biu";
resets = <&crg 0x9c 4>;
reset-names = "reset";
status = "disabled";
};
emmc: mmc@9830000 {
compatible = "hisilicon,hi3798mv200-dw-mshc";
reg = <0x9830000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_MMC_CIU_CLK>,
<&crg HISTB_MMC_BIU_CLK>,
<&crg HISTB_MMC_SAMPLE_CLK>,
<&crg HISTB_MMC_DRV_CLK>;
clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
resets = <&crg 0xa0 4>;
reset-names = "reset";
status = "disabled";
};
gmac: ethernet@9840000 {
compatible = "hisilicon,hi3798mv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9840000 0x1000>,
<0x984300c 0x4>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH0_MAC_CLK>,
<&crg HISTB_ETH0_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 0>,
<&crg 0xcc 2>,
<&crg 0xcc 5>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
ohci: ohci@9880000 {
compatible = "generic-ohci";
reg = <0x9880000 0x10000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_USB2_BUS_CLK>,
<&crg HISTB_USB2_12M_CLK>,
<&crg HISTB_USB2_48M_CLK>;
clock-names = "bus", "clk12", "clk48";
resets = <&crg 0xb8 12>;
reset-names = "bus";
status = "disabled";
};
ehci: ehci@9890000 {
compatible = "generic-ehci";
reg = <0x9890000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_USB2_BUS_CLK>,
<&crg HISTB_USB2_PHY_CLK>,
<&crg HISTB_USB2_UTMI_CLK>;
clock-names = "bus", "phy", "utmi";
resets = <&crg 0xb8 12>,
<&crg 0xb8 16>,
<&crg 0xb8 13>;
reset-names = "bus", "phy", "utmi";
phys = <&usb2_phy1>;
phy-names = "usb";
status = "disabled";
};
sd1: mmc@9c40000 {
compatible = "snps,dw-mshc";
reg = <0x9c40000 0x10000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_SDIO1_CIU_CLK>,
<&crg HISTB_SDIO1_BIU_CLK>;
clock-names = "ciu", "biu";
resets = <&crg 0x28c 4>;
reset-names = "reset";
status = "disabled";
};
};
};
|
