arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019, 2021 NXP
 */

#include "imx8mn-u-boot.dtsi"

&pinctrl_reg_usdhc2_vmmc {
	u-boot,dm-spl;
};

&reg_usdhc2_vmmc {
	u-boot,off-on-delay-us = <20000>;
};

&pinctrl_uart2 {
	u-boot,dm-spl;
};

&pinctrl_usdhc2_gpio {
	u-boot,dm-spl;
};

&pinctrl_usdhc2 {
	u-boot,dm-spl;
};

&pinctrl_usdhc3 {
	u-boot,dm-spl;
};

&pinctrl_wdog {
	u-boot,dm-spl;
};

&gpio1 {
	u-boot,dm-spl;
};

&gpio2 {
	u-boot,dm-spl;
};

&gpio3 {
	u-boot,dm-spl;
};

&gpio4 {
	u-boot,dm-spl;
};

&gpio5 {
	u-boot,dm-spl;
};

&uart2 {
	u-boot,dm-spl;
};

&crypto {
	u-boot,dm-spl;
};

&sec_jr0 {
	u-boot,dm-spl;
};

&sec_jr1 {
	u-boot,dm-spl;
};

&sec_jr2 {
	u-boot,dm-spl;
};

&usdhc1 {
	u-boot,dm-spl;
};

&usdhc2 {
	u-boot,dm-spl;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
};

&usdhc3 {
	u-boot,dm-spl;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
};