summaryrefslogtreecommitdiff
path: root/arch/arm/dts/imx8qm-rom7720-a1.dts
blob: 5f9ac955ed4c6256c8894442ed58fd9f617d515d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
// SPDX-License-Identifier:	GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 */

/dts-v1/;

/* First 128KB is for PSCI ATF. */
/memreserve/ 0x80000000 0x00020000;

#include "fsl-imx8qm.dtsi"

/ {
	model = "Advantech iMX8QM Qseven series";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
		stdout-path = &lpuart0;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;
		user {
			label = "heartbeat";
			gpios = <&gpio2 15 0>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usb_otg1_vbus: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "sw-3p3-sd1";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;

	imx8qm-mek {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000048
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
			>;
		};

		pinctrl_fec2: fec2grp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000041
				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000021
				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000021
				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000021
				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000021
				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000021
				/* WP */
				SC_P_USDHC2_WP_LSIO_GPIO4_IO11		0x00000021
				/* CD */
				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12	0x00000021
			>;
		};

		pinctrl_lpi2c1: lpi2c1grp {
			fsl,pins = <
				SC_P_GPT0_CLK_DMA_I2C1_SCL		0x06000020
				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0x06000020
				/*
				 * Change the default alt function from SCL/SDA to others,
				 * to avoid select input conflict with GPT0
				 */
				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x0700004c
				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x0700004c
				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x0700004c
				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x0700004c
			>;
		};

		pinctrl_gpio_leds: gpioledsgrp {
			fsl,pins = <
				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15		0x00000021
			>;
		};
	};
};

&gpio2 {
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&gpio5 {
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <4>;
	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,ar8031-phy-fixup;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	fsl,ar8031-phy-fixup;
	fsl,magic-packet;
	status = "okay";
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";

	pca9557_a: gpio@18 {
		compatible = "nxp,pca9557";
		reg = <0x18>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_b: gpio@19 {
		compatible = "nxp,pca9557";
		reg = <0x19>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_c: gpio@1b {
		compatible = "nxp,pca9557";
		reg = <0x1b>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_d: gpio@1f {
		compatible = "nxp,pca9557";
		reg = <0x1f>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart1 {
	status = "okay";
};