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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* T2080RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2021 NXP
*/
/include/ "t2080.dtsi"
/ {
model = "fsl,T2080RDB";
compatible = "fsl,T2080RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
spi0 = &espi0;
};
};
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&xg_aq1202_phy3>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&xg_aq1202_phy4>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
mdio@fd000 {
xg_cs4315_phy1: ethernet-phy@c {
compatible = "ethernet-phy-id13e5.1002";
reg = <0xc>;
};
xg_cs4315_phy2: ethernet-phy@d {
compatible = "ethernet-phy-id13e5.1002";
reg = <0xd>;
};
xg_aq1202_phy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
};
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor"; /* 16MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};
&i2c0 {
status = "okay";
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
/include/ "t2080si-post.dtsi"
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