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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2021 Tianrui Wei <tianrui-wei@outlook.com> */
/*
* This dts is for a dual core instance of OpenPiton+Ariane built
* to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
* are automatically generated by the OpenPiton build system and
* this configuration may not be what you need if your configuration
* is different from the below.
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "openpiton,riscv64";
chosen {
stdout-path = "uart0:115200";
};
aliases {
console = &uart0;
serial0 = &uart0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <520835>;
CPU0: cpu@0 {
clocks = <&clk0>;
u-boot,dm-spl;
device_type = "cpu";
reg = <0>;
compatible = "openhwgroup,cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU1: cpu@1 {
clocks = <&clk0>;
device_type = "cpu";
reg = <1>;
compatible = "openhwgroup,cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
clocks {
clk0: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <66667000>;
};
};
memory@80000000 {
u-boot,dm-spl;
device_type = "memory";
reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "openpiton,chipset", "simple-bus";
ranges;
uart0: uart@fff0c2c000 {
compatible = "ns16550", "openpiton,ns16550";
reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
interrupt-parent = <&PLIC0>;
interrupts = <1>;
reg-shift = <0>;
// regs are spaced on 8 bit boundary
};
eth: ethernet@fff0d00000 {
compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet";
device_type = "network";
reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
interrupt-parent = <&PLIC0>;
interrupts = <2>;
phy-handle = <&phy0>;
xlnx,duplex = <0x1>;
xlnx,include-global-buffers = <0x1>;
xlnx,include-internal-loopback = <0x0>;
xlnx,include-mdio = <0x1>;
xlnx,rx-ping-pong = <0x1>;
xlnx,s-axi-id-width = <0x1>;
xlnx,tx-ping-pong = <0x1>;
xlnx,use-internal = <0x0>;
axi_ethernetlite_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@1 {
compatible = "ethernet-phy-id001C.C915";
device_type = "ethernet-phy";
reg = <1>;
};
};
};
sdhci_0: sdhci@f000000000 {
u-boot,dm-spl;
compatible = "openpiton,piton-mmc", "openpiton,mmc";
reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
};
clint@fff1020000 {
compatible = "sifive,clint0", "openpiton,clint";
interrupts-extended = < &CPU0_intc 3
&CPU0_intc 7
&CPU1_intc 3
&CPU1_intc 7 >;
reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
clocks = <&clk0>;
};
PLIC0: plic@fff1100000 {
u-boot,dm-spl;
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0", "openpiton,plic";
interrupt-controller;
interrupts-extended = < &CPU0_intc 11
&CPU0_intc 9
&CPU1_intc 11
&CPU1_intc 9 >;
reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
riscv,max-priority = <7>;
riscv,ndev = <2>;
};
};
};
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