1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
|
// SPDX-License-Identifier: GPL-2.0
/*
* ZynqMP GPIO modepin driver
*
* Copyright (C) 2021 Xilinx, Inc.
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm.h>
#include <asm/arch/hardware.h>
#include <zynqmp_firmware.h>
#define OUTEN(pin) (BIT(0) << (pin))
#define INVAL(pin) (BIT(4) << (pin))
#define OUTVAL(pin) (BIT(8) << (pin))
#define ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK 0xF0F
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL (ZYNQMP_CRL_APB_BASEADDR + \
(0x250U))
static int get_gpio_modepin(u32 *ret_payload)
{
return xilinx_pm_request(PM_MMIO_READ, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
0, 0, 0, ret_payload);
}
static int set_gpio_modepin(int val)
{
return xilinx_pm_request(PM_MMIO_WRITE, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK,
val, 0, NULL);
}
static int modepin_gpio_direction_input(struct udevice *dev,
unsigned int offset)
{
return 0;
}
static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset,
int value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 out_val = 0;
int ret;
ret = get_gpio_modepin(ret_payload);
if (value)
out_val = OUTVAL(offset) | ret_payload[1];
else
out_val = ~OUTVAL(offset) & ret_payload[1];
return set_gpio_modepin(out_val);
}
static int modepin_gpio_direction_output(struct udevice *dev,
unsigned int offset, int value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 out_en = 0;
int ret;
ret = get_gpio_modepin(ret_payload);
if (ret)
return ret;
if (value)
out_en = OUTEN(offset) | ret_payload[1];
else
out_en = ~OUTEN(offset) & ret_payload[1];
ret = set_gpio_modepin(out_en);
if (ret)
return ret;
return modepin_gpio_set_value(dev, offset, value);
}
static int modepin_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
struct ofnode_phandle_args *args)
{
desc->offset = args->args[0];
return 0;
}
static int modepin_gpio_get_value(struct udevice *dev, unsigned int offset)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
ret = get_gpio_modepin(ret_payload);
if (ret)
return ret;
return (INVAL(offset) & ret_payload[1]) ? 1 : 0;
}
static int modepin_gpio_get_function(struct udevice *dev, unsigned int offset)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
ret = get_gpio_modepin(ret_payload);
if (ret)
return ret;
return (OUTEN(offset) & ret_payload[1]) ? GPIOF_OUTPUT : GPIOF_INPUT;
}
static const struct dm_gpio_ops modepin_gpio_ops = {
.direction_input = modepin_gpio_direction_input,
.direction_output = modepin_gpio_direction_output,
.get_value = modepin_gpio_get_value,
.set_value = modepin_gpio_set_value,
.get_function = modepin_gpio_get_function,
.xlate = modepin_gpio_xlate,
};
static int modepin_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
label_ptr = dev_read_prop(dev, "label", NULL);
if (label_ptr) {
uc_priv->bank_name = strdup(label_ptr);
if (!uc_priv->bank_name)
return -ENOMEM;
} else {
uc_priv->bank_name = dev->name;
}
uc_priv->gpio_count = 4;
return 0;
}
static const struct udevice_id modepin_gpio_ids[] = {
{ .compatible = "xlnx,zynqmp-gpio-modepin",},
{ }
};
U_BOOT_DRIVER(modepin_gpio) = {
.name = "modepin_gpio",
.id = UCLASS_GPIO,
.ops = &modepin_gpio_ops,
.of_match = modepin_gpio_ids,
.probe = modepin_gpio_probe,
};
|
