summaryrefslogtreecommitdiff
path: root/drivers/net/sun8i_emac.c
blob: 5a1b38bf80f48309f12931cc009306935673126e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2016
 * Author: Amit Singh Tomar, amittomer25@gmail.com
 *
 * Ethernet driver for H3/A64/A83T based SoC's
 *
 * It is derived from the work done by
 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
 *
*/

#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdt_support.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
#include <reset.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <wait_bit.h>
#if CONFIG_IS_ENABLED(DM_GPIO)
#include <asm-generic/gpio.h>
#endif

#define MDIO_CMD_MII_BUSY		BIT(0)
#define MDIO_CMD_MII_WRITE		BIT(1)

#define MDIO_CMD_MII_PHY_REG_ADDR_MASK	0x000001f0
#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT	4
#define MDIO_CMD_MII_PHY_ADDR_MASK	0x0001f000
#define MDIO_CMD_MII_PHY_ADDR_SHIFT	12
#define MDIO_CMD_MII_CLK_CSR_DIV_16	0x0
#define MDIO_CMD_MII_CLK_CSR_DIV_32	0x1
#define MDIO_CMD_MII_CLK_CSR_DIV_64	0x2
#define MDIO_CMD_MII_CLK_CSR_DIV_128	0x3
#define MDIO_CMD_MII_CLK_CSR_SHIFT	20

#define CONFIG_TX_DESCR_NUM	32
#define CONFIG_RX_DESCR_NUM	32
#define CONFIG_ETH_BUFSIZE	2048 /* Note must be dma aligned */

/*
 * The datasheet says that each descriptor can transfers up to 4096 bytes
 * But later, the register documentation reduces that value to 2048,
 * using 2048 cause strange behaviours and even BSP driver use 2047
 */
#define CONFIG_ETH_RXSIZE	2044 /* Note must fit in ETH_BUFSIZE */

#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)

#define H3_EPHY_DEFAULT_VALUE	0x58000
#define H3_EPHY_DEFAULT_MASK	GENMASK(31, 15)
#define H3_EPHY_ADDR_SHIFT	20
#define REG_PHY_ADDR_MASK	GENMASK(4, 0)
#define H3_EPHY_LED_POL		BIT(17)	/* 1: active low, 0: active high */
#define H3_EPHY_SHUTDOWN	BIT(16)	/* 1: shutdown, 0: power up */
#define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */

#define SC_RMII_EN		BIT(13)
#define SC_EPIT			BIT(2) /* 1: RGMII, 0: MII */
#define SC_ETCS_MASK		GENMASK(1, 0)
#define SC_ETCS_EXT_GMII	0x1
#define SC_ETCS_INT_GMII	0x2
#define SC_ETXDC_MASK		GENMASK(12, 10)
#define SC_ETXDC_OFFSET		10
#define SC_ERXDC_MASK		GENMASK(9, 5)
#define SC_ERXDC_OFFSET		5

#define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)

#define AHB_GATE_OFFSET_EPHY	0

/* IO mux settings */
#define SUN8I_IOMUX_H3		2
#define SUN8I_IOMUX_R40		5
#define SUN8I_IOMUX_H6		5
#define SUN8I_IOMUX_H616	2
#define SUN8I_IOMUX		4

/* H3/A64 EMAC Register's offset */
#define EMAC_CTL0		0x00
#define EMAC_CTL0_FULL_DUPLEX		BIT(0)
#define EMAC_CTL0_SPEED_MASK		GENMASK(3, 2)
#define EMAC_CTL0_SPEED_10		(0x2 << 2)
#define EMAC_CTL0_SPEED_100		(0x3 << 2)
#define EMAC_CTL0_SPEED_1000		(0x0 << 2)
#define EMAC_CTL1		0x04
#define EMAC_CTL1_SOFT_RST		BIT(0)
#define EMAC_CTL1_BURST_LEN_SHIFT	24
#define EMAC_INT_STA		0x08
#define EMAC_INT_EN		0x0c
#define EMAC_TX_CTL0		0x10
#define	EMAC_TX_CTL0_TX_EN		BIT(31)
#define EMAC_TX_CTL1		0x14
#define	EMAC_TX_CTL1_TX_MD		BIT(1)
#define	EMAC_TX_CTL1_TX_DMA_EN		BIT(30)
#define	EMAC_TX_CTL1_TX_DMA_START	BIT(31)
#define EMAC_TX_FLOW_CTL	0x1c
#define EMAC_TX_DMA_DESC	0x20
#define EMAC_RX_CTL0		0x24
#define	EMAC_RX_CTL0_RX_EN		BIT(31)
#define EMAC_RX_CTL1		0x28
#define	EMAC_RX_CTL1_RX_MD		BIT(1)
#define	EMAC_RX_CTL1_RX_RUNT_FRM	BIT(2)
#define	EMAC_RX_CTL1_RX_ERR_FRM		BIT(3)
#define	EMAC_RX_CTL1_RX_DMA_EN		BIT(30)
#define	EMAC_RX_CTL1_RX_DMA_START	BIT(31)
#define EMAC_RX_DMA_DESC	0x34
#define EMAC_MII_CMD		0x48
#define EMAC_MII_DATA		0x4c
#define EMAC_ADDR0_HIGH		0x50
#define EMAC_ADDR0_LOW		0x54
#define EMAC_TX_DMA_STA		0xb0
#define EMAC_TX_CUR_DESC	0xb4
#define EMAC_TX_CUR_BUF		0xb8
#define EMAC_RX_DMA_STA		0xc0
#define EMAC_RX_CUR_DESC	0xc4

#define EMAC_DESC_OWN_DMA	BIT(31)
#define EMAC_DESC_LAST_DESC	BIT(30)
#define EMAC_DESC_FIRST_DESC	BIT(29)
#define EMAC_DESC_CHAIN_SECOND	BIT(24)

#define EMAC_DESC_RX_ERROR_MASK	0x400068db

DECLARE_GLOBAL_DATA_PTR;

enum emac_variant {
	A83T_EMAC = 1,
	H3_EMAC,
	A64_EMAC,
	R40_GMAC,
	H6_EMAC,
};

struct emac_dma_desc {
	u32 status;
	u32 ctl_size;
	u32 buf_addr;
	u32 next;
} __aligned(ARCH_DMA_MINALIGN);

struct emac_eth_dev {
	struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
	struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
	char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
	char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);

	u32 interface;
	u32 phyaddr;
	u32 link;
	u32 speed;
	u32 duplex;
	u32 phy_configured;
	u32 tx_currdescnum;
	u32 rx_currdescnum;
	u32 addr;
	u32 tx_slot;
	bool use_internal_phy;

	enum emac_variant variant;
	void *mac_reg;
	phys_addr_t sysctl_reg;
	struct phy_device *phydev;
	struct mii_dev *bus;
	struct clk tx_clk;
	struct clk ephy_clk;
	struct reset_ctl tx_rst;
	struct reset_ctl ephy_rst;
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct gpio_desc reset_gpio;
#endif
};


struct sun8i_eth_pdata {
	struct eth_pdata eth_pdata;
	u32 reset_delays[3];
	int tx_delay_ps;
	int rx_delay_ps;
};


static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	struct udevice *dev = bus->priv;
	struct emac_eth_dev *priv = dev_get_priv(dev);
	u32 mii_cmd;
	int ret;

	mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
		MDIO_CMD_MII_PHY_REG_ADDR_MASK;
	mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
		MDIO_CMD_MII_PHY_ADDR_MASK;

	/*
	 * The EMAC clock is either 200 or 300 MHz, so we need a divider
	 * of 128 to get the MDIO frequency below the required 2.5 MHz.
	 */
	mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;

	mii_cmd |= MDIO_CMD_MII_BUSY;

	writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);

	ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
				MDIO_CMD_MII_BUSY, false,
				CONFIG_MDIO_TIMEOUT, true);
	if (ret < 0)
		return ret;

	return readl(priv->mac_reg + EMAC_MII_DATA);
}

static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
			    u16 val)
{
	struct udevice *dev = bus->priv;
	struct emac_eth_dev *priv = dev_get_priv(dev);
	u32 mii_cmd;

	mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
		MDIO_CMD_MII_PHY_REG_ADDR_MASK;
	mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
		MDIO_CMD_MII_PHY_ADDR_MASK;

	/*
	 * The EMAC clock is either 200 or 300 MHz, so we need a divider
	 * of 128 to get the MDIO frequency below the required 2.5 MHz.
	 */
	mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;

	mii_cmd |= MDIO_CMD_MII_WRITE;
	mii_cmd |= MDIO_CMD_MII_BUSY;

	writel(val, priv->mac_reg + EMAC_MII_DATA);
	writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);

	return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
				 MDIO_CMD_MII_BUSY, false,
				 CONFIG_MDIO_TIMEOUT, true);
}

static int sun8i_eth_write_hwaddr(struct udevice *dev)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	uchar *mac_id = pdata->enetaddr;
	u32 macid_lo, macid_hi;

	macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
		(mac_id[3] << 24);
	macid_hi = mac_id[4] + (mac_id[5] << 8);

	writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
	writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);

	return 0;
}

static void sun8i_adjust_link(struct emac_eth_dev *priv,
			      struct phy_device *phydev)
{
	u32 v;

	v = readl(priv->mac_reg + EMAC_CTL0);

	if (phydev->duplex)
		v |= EMAC_CTL0_FULL_DUPLEX;
	else
		v &= ~EMAC_CTL0_FULL_DUPLEX;

	v &= ~EMAC_CTL0_SPEED_MASK;

	switch (phydev->speed) {
	case 1000:
		v |= EMAC_CTL0_SPEED_1000;
		break;
	case 100:
		v |= EMAC_CTL0_SPEED_100;
		break;
	case 10:
		v |= EMAC_CTL0_SPEED_10;
		break;
	}
	writel(v, priv->mac_reg + EMAC_CTL0);
}

static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
{
	if (priv->use_internal_phy) {
		/* H3 based SoC's that has an Internal 100MBit PHY
		 * needs to be configured and powered up before use
		*/
		reg &= ~H3_EPHY_DEFAULT_MASK;
		reg |=  H3_EPHY_DEFAULT_VALUE;
		reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
		reg &= ~H3_EPHY_SHUTDOWN;
		return reg | H3_EPHY_SELECT;
	}

	/* This is to select External Gigabit PHY on those boards with
	 * an internal PHY. Does not hurt on other SoCs. Linux does
	 * it as well.
	 */
	return reg & ~H3_EPHY_SELECT;
}

static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
				 struct emac_eth_dev *priv)
{
	u32 reg;

	if (priv->variant == R40_GMAC) {
		/* Select RGMII for R40 */
		reg = readl(priv->sysctl_reg + 0x164);
		reg |= SC_ETCS_INT_GMII |
		       SC_EPIT |
		       (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);

		writel(reg, priv->sysctl_reg + 0x164);
		return 0;
	}

	reg = readl(priv->sysctl_reg + 0x30);

	reg = sun8i_emac_set_syscon_ephy(priv, reg);

	reg &= ~(SC_ETCS_MASK | SC_EPIT);
	if (priv->variant == H3_EMAC ||
	    priv->variant == A64_EMAC ||
	    priv->variant == H6_EMAC)
		reg &= ~SC_RMII_EN;

	switch (priv->interface) {
	case PHY_INTERFACE_MODE_MII:
		/* default */
		break;
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		reg |= SC_EPIT | SC_ETCS_INT_GMII;
		break;
	case PHY_INTERFACE_MODE_RMII:
		if (priv->variant == H3_EMAC ||
		    priv->variant == A64_EMAC ||
		    priv->variant == H6_EMAC) {
			reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
		break;
		}
		/* RMII not supported on A83T */
	default:
		debug("%s: Invalid PHY interface\n", __func__);
		return -EINVAL;
	}

	if (pdata->tx_delay_ps)
		reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
			 & SC_ETXDC_MASK;

	if (pdata->rx_delay_ps)
		reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
			 & SC_ERXDC_MASK;

	writel(reg, priv->sysctl_reg + 0x30);

	return 0;
}

static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
{
	struct phy_device *phydev;

	phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
	if (!phydev)
		return -ENODEV;

	phy_connect_dev(phydev, dev);

	priv->phydev = phydev;
	phy_config(priv->phydev);

	return 0;
}

#define cache_clean_descriptor(desc)					\
	flush_dcache_range((uintptr_t)(desc), 				\
			   (uintptr_t)(desc) + sizeof(struct emac_dma_desc))

#define cache_inv_descriptor(desc)					\
	invalidate_dcache_range((uintptr_t)(desc),			\
			       (uintptr_t)(desc) + sizeof(struct emac_dma_desc))

static void rx_descs_init(struct emac_eth_dev *priv)
{
	struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
	char *rxbuffs = &priv->rxbuffer[0];
	struct emac_dma_desc *desc_p;
	int i;

	/*
	 * Make sure we don't have dirty cache lines around, which could
	 * be cleaned to DRAM *after* the MAC has already written data to it.
	 */
	invalidate_dcache_range((uintptr_t)desc_table_p,
			      (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
	invalidate_dcache_range((uintptr_t)rxbuffs,
				(uintptr_t)rxbuffs + sizeof(priv->rxbuffer));

	for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
		desc_p = &desc_table_p[i];
		desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
		desc_p->next = (uintptr_t)&desc_table_p[i + 1];
		desc_p->ctl_size = CONFIG_ETH_RXSIZE;
		desc_p->status = EMAC_DESC_OWN_DMA;
	}

	/* Correcting the last pointer of the chain */
	desc_p->next = (uintptr_t)&desc_table_p[0];

	flush_dcache_range((uintptr_t)priv->rx_chain,
			   (uintptr_t)priv->rx_chain +
			sizeof(priv->rx_chain));

	writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
	priv->rx_currdescnum = 0;
}

static void tx_descs_init(struct emac_eth_dev *priv)
{
	struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
	char *txbuffs = &priv->txbuffer[0];
	struct emac_dma_desc *desc_p;
	int i;

	for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
		desc_p = &desc_table_p[i];
		desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
		desc_p->next = (uintptr_t)&desc_table_p[i + 1];
		desc_p->ctl_size = 0;
		desc_p->status = 0;
	}

	/* Correcting the last pointer of the chain */
	desc_p->next =  (uintptr_t)&desc_table_p[0];

	/* Flush the first TX buffer descriptor we will tell the MAC about. */
	cache_clean_descriptor(desc_table_p);

	writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
	priv->tx_currdescnum = 0;
}

static int sun8i_emac_eth_start(struct udevice *dev)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	int ret;

	/* Soft reset MAC */
	writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
	ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
				EMAC_CTL1_SOFT_RST, false, 10, true);
	if (ret) {
		printf("%s: Timeout\n", __func__);
		return ret;
	}

	/* Rewrite mac address after reset */
	sun8i_eth_write_hwaddr(dev);

	/* transmission starts after the full frame arrived in TX DMA FIFO */
	setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);

	/*
	 * RX DMA reads data from RX DMA FIFO to host memory after a
	 * complete frame has been written to RX DMA FIFO
	 */
	setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);

	/* DMA burst length */
	writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);

	/* Initialize rx/tx descriptors */
	rx_descs_init(priv);
	tx_descs_init(priv);

	/* PHY Start Up */
	ret = phy_startup(priv->phydev);
	if (ret)
		return ret;

	sun8i_adjust_link(priv, priv->phydev);

	/* Start RX/TX DMA */
	setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
		     EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
	setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);

	/* Enable RX/TX */
	setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
	setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);

	return 0;
}

static int parse_phy_pins(struct udevice *dev)
{
	int offset;
	const char *pin_name;
	int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
	u32 iomux;

	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
				       "pinctrl-0");
	if (offset < 0) {
		printf("WARNING: emac: cannot find pinctrl-0 node\n");
		return offset;
	}

	drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
					     "drive-strength", ~0);
	if (drive != ~0) {
		if (drive <= 10)
			drive = SUN4I_PINCTRL_10_MA;
		else if (drive <= 20)
			drive = SUN4I_PINCTRL_20_MA;
		else if (drive <= 30)
			drive = SUN4I_PINCTRL_30_MA;
		else
			drive = SUN4I_PINCTRL_40_MA;
	}

	if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
		pull = SUN4I_PINCTRL_PULL_UP;
	else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
		pull = SUN4I_PINCTRL_PULL_DOWN;

	/*
	 * The GPIO pinmux value is an integration choice, so depends on the
	 * SoC, not the EMAC variant.
	 */
	if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
		iomux = SUN8I_IOMUX_H3;
	else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
		iomux = SUN8I_IOMUX_R40;
	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
		iomux = SUN8I_IOMUX_H6;
	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
		iomux = SUN8I_IOMUX_H616;
	else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
		iomux = SUN8I_IOMUX;
	else if (IS_ENABLED(CONFIG_MACH_SUN50I))
		iomux = SUN8I_IOMUX;
	else
		BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");

	for (i = 0; ; i++) {
		int pin;

		pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
					      "pins", i, NULL);
		if (!pin_name)
			break;

		pin = sunxi_name_to_gpio(pin_name);
		if (pin < 0)
			continue;

		sunxi_gpio_set_cfgpin(pin, iomux);

		if (drive != ~0)
			sunxi_gpio_set_drv(pin, drive);
		if (pull != ~0)
			sunxi_gpio_set_pull(pin, pull);
	}

	if (!i) {
		printf("WARNING: emac: cannot find pins property\n");
		return -2;
	}

	return 0;
}

static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	u32 status, desc_num = priv->rx_currdescnum;
	struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
	uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
	int length;

	/* Invalidate entire buffer descriptor */
	cache_inv_descriptor(desc_p);

	status = desc_p->status;

	/* Check for DMA own bit */
	if (status & EMAC_DESC_OWN_DMA)
		return -EAGAIN;

	length = (status >> 16) & 0x3fff;

	/* make sure we read from DRAM, not our cache */
	invalidate_dcache_range(data_start,
				data_start + roundup(length, ARCH_DMA_MINALIGN));

	if (status & EMAC_DESC_RX_ERROR_MASK) {
		debug("RX: packet error: 0x%x\n",
		      status & EMAC_DESC_RX_ERROR_MASK);
		return 0;
	}
	if (length < 0x40) {
		debug("RX: Bad Packet (runt)\n");
		return 0;
	}

	if (length > CONFIG_ETH_RXSIZE) {
		debug("RX: Too large packet (%d bytes)\n", length);
		return 0;
	}

	*packetp = (uchar *)(ulong)desc_p->buf_addr;

	return length;
}

static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	u32 desc_num = priv->tx_currdescnum;
	struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
	uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
	uintptr_t data_end = data_start +
		roundup(length, ARCH_DMA_MINALIGN);

	desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;

	memcpy((void *)data_start, packet, length);

	/* Flush data to be sent */
	flush_dcache_range(data_start, data_end);

	/* frame begin and end */
	desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
	desc_p->status = EMAC_DESC_OWN_DMA;

	/* make sure the MAC reads the actual data from DRAM */
	cache_clean_descriptor(desc_p);

	/* Move to next Descriptor and wrap around */
	if (++desc_num >= CONFIG_TX_DESCR_NUM)
		desc_num = 0;
	priv->tx_currdescnum = desc_num;

	/* Start the DMA */
	setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);

	/*
	 * Since we copied the data above, we return here without waiting
	 * for the packet to be actually send out.
	 */

	return 0;
}

static int sun8i_emac_board_setup(struct udevice *dev,
				  struct emac_eth_dev *priv)
{
	int ret;

	ret = clk_enable(&priv->tx_clk);
	if (ret) {
		dev_err(dev, "failed to enable TX clock\n");
		return ret;
	}

	if (reset_valid(&priv->tx_rst)) {
		ret = reset_deassert(&priv->tx_rst);
		if (ret) {
			dev_err(dev, "failed to deassert TX reset\n");
			goto err_tx_clk;
		}
	}

	/* Only H3/H5 have clock controls for internal EPHY */
	if (clk_valid(&priv->ephy_clk)) {
		ret = clk_enable(&priv->ephy_clk);
		if (ret) {
			dev_err(dev, "failed to enable EPHY TX clock\n");
			return ret;
		}
	}

	if (reset_valid(&priv->ephy_rst)) {
		ret = reset_deassert(&priv->ephy_rst);
		if (ret) {
			dev_err(dev, "failed to deassert EPHY TX clock\n");
			return ret;
		}
	}

	return 0;

err_tx_clk:
	clk_disable(&priv->tx_clk);
	return ret;
}

#if CONFIG_IS_ENABLED(DM_GPIO)
static int sun8i_mdio_reset(struct mii_dev *bus)
{
	struct udevice *dev = bus->priv;
	struct emac_eth_dev *priv = dev_get_priv(dev);
	struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
	int ret;

	if (!dm_gpio_is_valid(&priv->reset_gpio))
		return 0;

	/* reset the phy */
	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
	if (ret)
		return ret;

	udelay(pdata->reset_delays[0]);

	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
	if (ret)
		return ret;

	udelay(pdata->reset_delays[1]);

	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
	if (ret)
		return ret;

	udelay(pdata->reset_delays[2]);

	return 0;
}
#endif

static int sun8i_mdio_init(const char *name, struct udevice *priv)
{
	struct mii_dev *bus = mdio_alloc();

	if (!bus) {
		debug("Failed to allocate MDIO bus\n");
		return -ENOMEM;
	}

	bus->read = sun8i_mdio_read;
	bus->write = sun8i_mdio_write;
	snprintf(bus->name, sizeof(bus->name), name);
	bus->priv = (void *)priv;
#if CONFIG_IS_ENABLED(DM_GPIO)
	bus->reset = sun8i_mdio_reset;
#endif

	return  mdio_register(bus);
}

static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
			      int length)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	u32 desc_num = priv->rx_currdescnum;
	struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];

	/* give the current descriptor back to the MAC */
	desc_p->status |= EMAC_DESC_OWN_DMA;

	/* Flush Status field of descriptor */
	cache_clean_descriptor(desc_p);

	/* Move to next desc and wrap-around condition. */
	if (++desc_num >= CONFIG_RX_DESCR_NUM)
		desc_num = 0;
	priv->rx_currdescnum = desc_num;

	return 0;
}

static void sun8i_emac_eth_stop(struct udevice *dev)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);

	/* Stop Rx/Tx transmitter */
	clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
	clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);

	/* Stop RX/TX DMA */
	clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
	clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);

	phy_shutdown(priv->phydev);
}

static int sun8i_emac_eth_probe(struct udevice *dev)
{
	struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
	struct emac_eth_dev *priv = dev_get_priv(dev);
	int ret;

	priv->mac_reg = (void *)pdata->iobase;

	ret = sun8i_emac_board_setup(dev, priv);
	if (ret)
		return ret;

	sun8i_emac_set_syscon(sun8i_pdata, priv);

	sun8i_mdio_init(dev->name, dev);
	priv->bus = miiphy_get_dev_by_name(dev->name);

	return sun8i_phy_init(priv, dev);
}

static const struct eth_ops sun8i_emac_eth_ops = {
	.start                  = sun8i_emac_eth_start,
	.write_hwaddr           = sun8i_eth_write_hwaddr,
	.send                   = sun8i_emac_eth_send,
	.recv                   = sun8i_emac_eth_recv,
	.free_pkt               = sun8i_eth_free_pkt,
	.stop                   = sun8i_emac_eth_stop,
};

static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
{
	struct ofnode_phandle_args phandle;
	int ret;

	ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
					     NULL, 0, 0, &phandle);
	if (ret)
		return ret;

	/* If the PHY node is not a child of the internal MDIO bus, we are
	 * using some external PHY.
	 */
	if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
					 "allwinner,sun8i-h3-mdio-internal"))
		return 0;

	ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
	if (ret) {
		dev_err(dev, "failed to get EPHY TX clock\n");
		return ret;
	}

	ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
	if (ret) {
		dev_err(dev, "failed to get EPHY TX reset\n");
		return ret;
	}

	priv->use_internal_phy = true;

	return 0;
}

static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
{
	struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
	struct emac_eth_dev *priv = dev_get_priv(dev);
	const char *phy_mode;
	const fdt32_t *reg;
	int node = dev_of_offset(dev);
	int offset = 0;
#if CONFIG_IS_ENABLED(DM_GPIO)
	int reset_flags = GPIOD_IS_OUT;
#endif
	int ret;

	pdata->iobase = dev_read_addr(dev);
	if (pdata->iobase == FDT_ADDR_T_NONE) {
		debug("%s: Cannot find MAC base address\n", __func__);
		return -EINVAL;
	}

	priv->variant = dev_get_driver_data(dev);

	if (!priv->variant) {
		printf("%s: Missing variant\n", __func__);
		return -EINVAL;
	}

	ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
	if (ret) {
		dev_err(dev, "failed to get TX clock\n");
		return ret;
	}

	ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
	if (ret && ret != -ENOENT) {
		dev_err(dev, "failed to get TX reset\n");
		return ret;
	}

	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
	if (offset < 0) {
		debug("%s: cannot find syscon node\n", __func__);
		return -EINVAL;
	}

	reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
	if (!reg) {
		debug("%s: cannot find reg property in syscon node\n",
		      __func__);
		return -EINVAL;
	}
	priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
						 offset, reg);
	if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
		debug("%s: Cannot find syscon base address\n", __func__);
		return -EINVAL;
	}

	pdata->phy_interface = -1;
	priv->phyaddr = -1;
	priv->use_internal_phy = false;

	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
	if (offset < 0) {
		debug("%s: Cannot find PHY address\n", __func__);
		return -EINVAL;
	}
	priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);

	phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);

	if (phy_mode)
		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	printf("phy interface%d\n", pdata->phy_interface);

	if (pdata->phy_interface == -1) {
		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
		return -EINVAL;
	}

	if (priv->variant == H3_EMAC) {
		ret = sun8i_handle_internal_phy(dev, priv);
		if (ret)
			return ret;
	}

	priv->interface = pdata->phy_interface;

	if (!priv->use_internal_phy)
		parse_phy_pins(dev);

	sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
						  "allwinner,tx-delay-ps", 0);
	if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
		printf("%s: Invalid TX delay value %d\n", __func__,
		       sun8i_pdata->tx_delay_ps);

	sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
						  "allwinner,rx-delay-ps", 0);
	if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
		printf("%s: Invalid RX delay value %d\n", __func__,
		       sun8i_pdata->rx_delay_ps);

#if CONFIG_IS_ENABLED(DM_GPIO)
	if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
			    "snps,reset-active-low"))
		reset_flags |= GPIOD_ACTIVE_LOW;

	ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
				   &priv->reset_gpio, reset_flags);

	if (ret == 0) {
		ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
					   "snps,reset-delays-us",
					   sun8i_pdata->reset_delays, 3);
	} else if (ret == -ENOENT) {
		ret = 0;
	}
#endif

	return 0;
}

static const struct udevice_id sun8i_emac_eth_ids[] = {
	{.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
	{.compatible = "allwinner,sun50i-a64-emac",
		.data = (uintptr_t)A64_EMAC },
	{.compatible = "allwinner,sun8i-a83t-emac",
		.data = (uintptr_t)A83T_EMAC },
	{.compatible = "allwinner,sun8i-r40-gmac",
		.data = (uintptr_t)R40_GMAC },
	{.compatible = "allwinner,sun50i-h6-emac",
		.data = (uintptr_t)H6_EMAC },
	{ }
};

U_BOOT_DRIVER(eth_sun8i_emac) = {
	.name   = "eth_sun8i_emac",
	.id     = UCLASS_ETH,
	.of_match = sun8i_emac_eth_ids,
	.of_to_plat = sun8i_emac_eth_of_to_plat,
	.probe  = sun8i_emac_eth_probe,
	.ops    = &sun8i_emac_eth_ops,
	.priv_auto	= sizeof(struct emac_eth_dev),
	.plat_auto	= sizeof(struct sun8i_eth_pdata),
	.flags = DM_FLAG_ALLOC_PRIV_DMA,
};