1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Starfive, Inc.
* Author: samin <samin.guo@starfivetech.com>
* yanhong <yanhong.wang@starfivetech.com>
*
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <reset-uclass.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <dt-bindings/reset/starfive-jh7110.h>
#define AONCRG_RESET_ASSERT 0x38
#define AONCRG_RESET_STATUS 0x3C
#define ISPCRG_RESET_ASSERT 0x38
#define ISPCRG_RESET_STATUS 0x3C
#define VOUTCRG_RESET_ASSERT 0x48
#define VOUTCRG_RESET_STATUS 0x4C
#define STGCRG_RESET_ASSERT 0x74
#define STGCRG_RESET_STATUS 0x78
#define SYSCRG_RESET_ASSERT0 0x2F8
#define SYSCRG_RESET_ASSERT1 0x2FC
#define SYSCRG_RESET_ASSERT2 0x300
#define SYSCRG_RESET_ASSERT3 0x304
#define SYSCRG_RESET_STATUS0 0x308
#define SYSCRG_RESET_STATUS1 0x30C
#define SYSCRG_RESET_STATUS2 0x310
#define SYSCRG_RESET_STATUS3 0x314
struct reset_assert_t {
void __iomem *assert;
void __iomem *status;
};
enum JH7110_RESET_CRG_GROUP {
SYSCRG_0 = 0,
SYSCRG_1,
SYSCRG_2,
SYSCRG_3,
STGCRG,
AONCRG,
ISPCRG,
VOUTCRG,
};
struct jh7110_reset_priv {
void __iomem *syscrg;
void __iomem *stgcrg;
void __iomem *aoncrg;
void __iomem *ispcrg;
void __iomem *voutcrg;
};
static const u32 jh7110_reset_asserted[8] = {
/* SYSCRG_STATUS0 */
BIT(RSTN_U0_U7MC_RST_BUS % 32) |
BIT(RSTN_U0_U7MC_CORE0 % 32) |
BIT(RSTN_U0_U7MC_CORE1 % 32) |
BIT(RSTN_U0_U7MC_CORE2 % 32) |
BIT(RSTN_U0_U7MC_CORE3 % 32) |
BIT(RSTN_U0_U7MC_CORE4 % 32),
/* SYSCRG_STATUS1 */
0,
/* SYSCRG_STATUS2 */
0,
/* SYSCRG_STATUS3 */
0,
/* STGCRG */
BIT(RSTN_U0_HIFI4_CORE % 32) |
BIT(RSTN_U0_E24_CORE % 32),
/* AONCRG */
0,
/* ISPCRG */
0,
/*VOUTCRG*/
0,
};
static int jh7110_get_reset(struct jh7110_reset_priv *priv,
struct reset_assert_t *reset,
unsigned long group)
{
switch (group) {
case SYSCRG_0:
reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT0;
reset->status = priv->syscrg + SYSCRG_RESET_STATUS0;
break;
case SYSCRG_1:
reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT1;
reset->status = priv->syscrg + SYSCRG_RESET_STATUS1;
break;
case SYSCRG_2:
reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT2;
reset->status = priv->syscrg + SYSCRG_RESET_STATUS2;
break;
case SYSCRG_3:
reset->assert = priv->syscrg + SYSCRG_RESET_ASSERT3;
reset->status = priv->syscrg + SYSCRG_RESET_STATUS3;
break;
case STGCRG:
reset->assert = priv->stgcrg + STGCRG_RESET_ASSERT;
reset->status = priv->stgcrg + STGCRG_RESET_STATUS;
break;
case AONCRG:
reset->assert = priv->aoncrg + AONCRG_RESET_ASSERT;
reset->status = priv->aoncrg + AONCRG_RESET_STATUS;
break;
case ISPCRG:
reset->assert = priv->ispcrg + ISPCRG_RESET_ASSERT;
reset->status = priv->ispcrg + ISPCRG_RESET_STATUS;
break;
case VOUTCRG:
reset->assert = priv->voutcrg + VOUTCRG_RESET_ASSERT;
reset->status = priv->voutcrg + VOUTCRG_RESET_STATUS;
break;
default:
return -EINVAL;
}
return 0;
}
static int jh7110_reset_trigger(struct jh7110_reset_priv *priv,
unsigned long id, bool assert)
{
struct reset_assert_t reset;
unsigned long group;
u32 mask, value, done;
int ret;
group = id / 32;
mask = BIT(id % 32);
ret = jh7110_get_reset(priv, &reset, group);
if (ret) {
debug("reset: bad reset id.\n");
return ret;
}
done = jh7110_reset_asserted[group] & mask;
if (!assert)
done ^= mask;
value = readl(reset.assert);
if (assert)
value |= mask;
else
value &= ~mask;
writel(value, reset.assert);
/* if the associated clock is gated, deasserting might otherwise hang forever */
ret = readl_poll_timeout(reset.status, value, (value & mask) == done, 100000);
if (ret)
debug("reset %ld: timeout.\n", id);
return ret;
}
static int jh7110_reset_assert(struct reset_ctl *rst)
{
struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
jh7110_reset_trigger(priv, rst->id, true);
return 0;
}
static int jh7110_reset_deassert(struct reset_ctl *rst)
{
struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
jh7110_reset_trigger(priv, rst->id, false);
return 0;
}
static int jh7110_reset_free(struct reset_ctl *rst)
{
return 0;
}
static int jh7110_reset_request(struct reset_ctl *rst)
{
if (rst->id >= RSTN_JH7110_RESET_END)
return -EINVAL;
return 0;
}
struct reset_ops jh7110_reset_reset_ops = {
.rfree = jh7110_reset_free,
.request = jh7110_reset_request,
.rst_assert = jh7110_reset_assert,
.rst_deassert = jh7110_reset_deassert,
};
static const struct udevice_id jh7110_reset_ids[] = {
{ .compatible = "starfive,jh7110-reset" },
{ /* sentinel */ }
};
static int jh7110_reset_probe(struct udevice *dev)
{
struct jh7110_reset_priv *priv = dev_get_priv(dev);
priv->syscrg = dev_remap_addr_name(dev, "syscrg");
if (!priv->syscrg)
return -EINVAL;
priv->stgcrg = dev_remap_addr_name(dev, "stgcrg");
if (!priv->stgcrg)
return -EINVAL;
priv->aoncrg = dev_remap_addr_name(dev, "aoncrg");
if (!priv->aoncrg)
return -EINVAL;
priv->ispcrg = dev_remap_addr_name(dev, "ispcrg");
if (!priv->ispcrg)
return -EINVAL;
priv->voutcrg = dev_remap_addr_name(dev, "voutcrg");
if (!priv->voutcrg)
return -EINVAL;
return 0;
}
U_BOOT_DRIVER(jh7110_reset) = {
.name = "jh7110-reset",
.id = UCLASS_RESET,
.of_match = jh7110_reset_ids,
.ops = &jh7110_reset_reset_ops,
.probe = jh7110_reset_probe,
.priv_auto = sizeof(struct jh7110_reset_priv),
};
|