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| author | Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com> | 2022-05-11 01:47:45 +0300 |
|---|---|---|
| committer | Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com> | 2022-05-20 14:49:59 +0300 |
| commit | ab986eaa298cbc5ef8af58cc44f947b2620699e4 (patch) | |
| tree | a98c85ac100a7c1cf6da10412473ee1d5ad650fd | |
| parent | 8dcd772516812e8dd37fdf748b1724726b9fd31d (diff) | |
| download | linux-ab986eaa298cbc5ef8af58cc44f947b2620699e4.tar.xz | |
i3c: dw: master: Enable PEC support in hardware
DWC MIPI I3C Controller supports automatic PEC generation and
validation for private write and read SDR transfers. This feature
could be used for upper layers, e.g. MCTP over I3C to offload PEC
handling to the hardware.
PEC supported by DWC MIPI I3C Controller is described in JESD403-1.
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
| -rw-r--r-- | drivers/i3c/master/dw-i3c-master.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c index f67ff56febc8..1863f6dc65d9 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -36,6 +36,7 @@ #define HW_CAPABILITY 0x8 #define COMMAND_QUEUE_PORT 0xc +#define COMMAND_PORT_PEC BIT(31) #define COMMAND_PORT_TOC BIT(30) #define COMMAND_PORT_READ_TRANSFER BIT(28) #define COMMAND_PORT_SDAP BIT(27) @@ -1487,6 +1488,9 @@ static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev, if (i == (i3c_nxfers - 1)) cmd->cmd_lo |= COMMAND_PORT_TOC; + if (dev->info.pec) + cmd->cmd_lo |= COMMAND_PORT_PEC; + dev_dbg(master->dev, "%s:cmd_hi=0x%08x cmd_lo=0x%08x tx_len=%d rx_len=%d\n", __func__, cmd->cmd_hi, cmd->cmd_lo, cmd->tx_len, @@ -2189,6 +2193,8 @@ static int dw_i3c_probe(struct platform_device *pdev) dw_i3c_master_of_timings(master, pdev->dev.of_node); + master->base.pec_supported = true; + ret = i3c_register(&master->base, &pdev->dev, &dw_mipi_i3c_ops, &dw_mipi_i3c_target_ops, false); if (ret) |