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| author | Peter Yin <peter.yin@quantatw.com> | 2024-05-07 18:24:26 +0300 |
|---|---|---|
| committer | Patrick Williams <patrick@stwcx.xyz> | 2024-05-14 01:08:34 +0300 |
| commit | 9761ec6cef983545c03b97e16a9a87b6c35a0dd8 (patch) | |
| tree | c0e61846c12182fd268d7f27567dc60bdaf990d7 /meta-facebook | |
| parent | a1772f0e47220e264a350ec8e628eabe7de0a31d (diff) | |
| download | openbmc-9761ec6cef983545c03b97e16a9a87b6c35a0dd8.tar.xz | |
meta-facebook: harma: support 2nd HSC sled cycle.
To support sled cycle for 2ND HSC source.
Change-Id: Id51a7cf310d45db31572540d35bee7b7ab780ca6
Signed-off-by: Peter Yin <peter.yin@quantatw.com>
Diffstat (limited to 'meta-facebook')
| -rw-r--r-- | meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/chassis-powercycle | 46 |
1 files changed, 28 insertions, 18 deletions
diff --git a/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/chassis-powercycle b/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/chassis-powercycle index 295982dc56..b0297745ac 100644 --- a/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/chassis-powercycle +++ b/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/chassis-powercycle @@ -5,24 +5,34 @@ source /usr/libexec/phosphor-state-manager/power-cmd #Sled cycle echo "Starting Chassis Power Cycle" -# LTC4287 MFR_REBOOT_CONTROL (FDh) Read/Write -# [3]: -# REBOOT 0 Write a 1 to reboot. -# [2:0] -# RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1 -# RBT_DL[2:0] DELAY -# 000 0.580 s -# 001 1.16 s -# 010 2.32 s -# 011 4.64 s -# 100 9.28 s -# 101 18.6 s -# 110 37.1 s -# 111 74.2 s -ltc4287-chassis-power-cycle() { - i2cset -f -y 4 0x44 0xfd 0x04 - i2cset -f -y 4 0x44 0xfd 0x0e + +chassis-power-cycle() { + # XDP710 + ret1=$(i2cset -f -y 4 0x40 0xEC) + + # LTC4287 MFR_REBOOT_CONTROL (FDh) Read/Write + # [3]: + # REBOOT 0 Write a 1 to reboot. + # [2:0] + # RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1 + # RBT_DL[2:0] DELAY + # 000 0.580 s + # 001 1.16 s + # 010 2.32 s + # 011 4.64 s + # 100 9.28 s + # 101 18.6 s + # 110 37.1 s + # 111 74.2 s + ret2=$(i2cset -f -y 4 0x44 0xfd 0x04) + ret3=$(i2cset -f -y 4 0x44 0xfd 0x0e) + + if [ "$ret1" -ne 0 ] && { [ "$ret2" -ne 0 ] || [ "$ret3" -ne 0 ]; }; then + return 1 + else + return 0 + fi } echo "Starting Chassis Power Cycle" -ltc4287-chassis-power-cycle +chassis-power-cycle |