Merge branch 'starfive-6.6.10-dubhe-emphasize-l2-cache-compatibility' into 'starfive-6.6.10-dubhe'REL_DUBHE_MAR2024starfive-6.6.10-dubhe

cache: dubhe: emphasize controller's L2 cache compatibility

See merge request starfive-tech/linux!276

6 files changed, 22 insertions, 22 deletions

diff --git a/Documentation/devicetree/bindings/cache/starfive,dubhe-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,dubhe-l2cache.yaml
index 64dd7020a4f4..87fd2c02d7ec 100644
--- a/Documentation/devicetree/bindings/cache/starfive,dubhe-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/starfive,dubhe-l2cache.yaml
@@ -1,24 +1,24 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/cache/starfive,dubhe-cache.yaml#
+$id: http://devicetree.org/schemas/cache/starfive,dubhe-l2cache.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: StarFive Dubhe Cache Controller
+title: StarFive Dubhe L2 Cache Controller
 
 maintainers:
   - Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
 
 description:
-  StarFive Dubhe Cache Controller implementation predates the RISC-V CMO ISA
-  extension. Dubhe vendor specific implementation is put in place to handle
-  non-coherent DMA operation through a shared global memory pool.
+  StarFive Dubhe L2 Cache Controller implementation predates the RISC-V CMO
+  ISA extension. Dubhe vendor specific implementation is put in place to
+  handle non-coherent DMA operation through a shared global memory pool.
 
 properties:
   compatible:
     items:
       - enum:
-          - starfive,dubhe-cache
+          - starfive,dubhe-l2cache
       - const: cache
 
   cache-block-size:
@@ -48,7 +48,7 @@ required:
 examples:
   - |
     cache-controller {
-        compatible = "starfive,dubhe-cache", "cache";
+        compatible = "starfive,dubhe-l2cache", "cache";
         cache-block-size = <64>;
         cache-level = <2>;
         cache-sets = <4096>;
diff --git a/arch/riscv/boot/dts/starfive/dubhe80.dtsi b/arch/riscv/boot/dts/starfive/dubhe80.dtsi
index 9031457ac7de..dad10fb86eef 100644
--- a/arch/riscv/boot/dts/starfive/dubhe80.dtsi
+++ b/arch/riscv/boot/dts/starfive/dubhe80.dtsi
@@ -34,13 +34,13 @@
 };
 
 &l2_cache0 {
-	compatible = "starfive,dubhe-cache", "cache";
+	compatible = "starfive,dubhe-l2cache", "cache";
 	cache-sets = <512>;
 	cache-size = <0x40000>;
 };
 
 &l2_cache1 {
-	compatible = "starfive,dubhe-cache", "cache";
+	compatible = "starfive,dubhe-l2cache", "cache";
 	cache-sets = <512>;
 	cache-size = <0x40000>;
 };
diff --git a/arch/riscv/boot/dts/starfive/dubhe90.dtsi b/arch/riscv/boot/dts/starfive/dubhe90.dtsi
index b75f2b0c1026..08878898667b 100644
--- a/arch/riscv/boot/dts/starfive/dubhe90.dtsi
+++ b/arch/riscv/boot/dts/starfive/dubhe90.dtsi
@@ -34,7 +34,7 @@
 };
 
 &l2_cache0 {
-	compatible = "starfive,dubhe-cache", "cache";
+	compatible = "starfive,dubhe-l2cache", "cache";
 	cache-sets = <4096>;
 	cache-size = <0x200000>;
 };
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index e6b14709a085..9bbe15cd898f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,8 +13,8 @@ config STARFIVE_DUBHE_L2_CACHE
 	depends on ARCH_STARFIVE
 	select RISCV_NONSTANDARD_CACHE_OPS
 	help
-	  Support for the cache controller on StarFive platforms.
-	  StarFive Dubhe Cache Controller implementation predates
+	  Support for the L2 cache controller on StarFive platforms.
+	  StarFive Dubhe L2 cache controller implementation predates
 	  RISC-V CMO ISA extension. This allow vendor specific
 	  implementation to handle non-coherent DMA through global
 	  memory pool.
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index feb806c141b0..916e6a6fcef1 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
-obj-$(CONFIG_STARFIVE_DUBHE_L2_CACHE) += starfive_dubhe_cache.o
\ No newline at end of file
+obj-$(CONFIG_STARFIVE_DUBHE_L2_CACHE) += starfive_dubhe_l2cache.o
\ No newline at end of file
diff --git a/drivers/cache/starfive_dubhe_cache.c b/drivers/cache/starfive_dubhe_l2cache.c
index 79f8b908238b..b8aec05d37c6 100644
--- a/drivers/cache/starfive_dubhe_cache.c
+++ b/drivers/cache/starfive_dubhe_l2cache.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * StarFive cache controller driver
+ * StarFive L2 cache controller driver
  *
  * Copyright (C) 2023 StarFive Technology Co., Ltd.
  *
@@ -18,26 +18,26 @@ enum starfive_sbi_ext_fid {
 	STARFIVE_SBI_EXT_L2_INVALIDATE,
 };
 
-static void sbi_cache_flush(phys_addr_t paddr, size_t size)
+static void sbi_l2cache_flush(phys_addr_t paddr, size_t size)
 {
 	sbi_ecall(STARFIVE_SBI_EXT, STARFIVE_SBI_EXT_L2_FLUSH,
 		  paddr, size, 0, 0, 0, 0);
 }
 
-static void sbi_cache_invalidate(phys_addr_t paddr, size_t size)
+static void sbi_l2cache_invalidate(phys_addr_t paddr, size_t size)
 {
 	sbi_ecall(STARFIVE_SBI_EXT, STARFIVE_SBI_EXT_L2_INVALIDATE,
 		  paddr, size, 0, 0, 0, 0);
 }
 
 static const struct riscv_nonstd_cache_ops dubhe_cmo_ops __initdata = {
-	.wback = &sbi_cache_flush,
-	.inv = &sbi_cache_invalidate,
-	.wback_inv = &sbi_cache_invalidate,
+	.wback = &sbi_l2cache_flush,
+	.inv = &sbi_l2cache_invalidate,
+	.wback_inv = &sbi_l2cache_invalidate,
 };
 
-static const struct of_device_id starfive_cache_ids[] = {
-	{ .compatible = "starfive,dubhe-cache" },
+static const struct of_device_id starfive_l2cache_ids[] = {
+	{ .compatible = "starfive,dubhe-l2cache" },
 	{ /* end of table */ }
 };
 
@@ -45,7 +45,7 @@ static int __init starfive_cache_init(void)
 {
 	struct device_node *np;
 
-	np = of_find_matching_node(NULL, starfive_cache_ids);
+	np = of_find_matching_node(NULL, starfive_l2cache_ids);
 	if (!of_device_is_available(np))
 		return -ENODEV;