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| author | Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2023-07-22 17:36:17 +0300 |
|---|---|---|
| committer | Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2024-04-13 23:33:33 +0300 |
| commit | e25b469367343a650799c8da14daa9c1f2a1ecad (patch) | |
| tree | 65bc566f62956790671b8538e1a2161bac282621 | |
| parent | 9581f839eb19a47a66b18133f7ff1855a4315316 (diff) | |
| download | linux-e25b469367343a650799c8da14daa9c1f2a1ecad.tar.xz | |
riscv: dts: starfive: Add JH7100 USB node
Add the device tree node for the USB 3.0 peripheral on the
StarFive JH7100 SoC.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100-common.dtsi | 5 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 26 |
2 files changed, 31 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index ae1a6aeb0aea..98da35d95094 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -398,3 +398,8 @@ pinctrl-0 = <&uart3_pins>; status = "okay"; }; + +&usb3 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 1e7f33dcdf2f..7fc7bf6b3830 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -255,6 +255,32 @@ #reset-cells = <1>; }; + usb3: usb@104c0000 { + compatible = "starfive,jh7100-usb"; + ranges = <0x0 0x0 0x104c0000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&audclk JH7100_AUDCLK_USB_LPM>, + <&audclk JH7100_AUDCLK_USB_STB>, + <&clkgen JH7100_CLK_USB_AXI>, + <&clkgen JH7100_CLK_USBNOC_AXI>; + clock-names = "lpm", "stb", "axi", "nocaxi"; + resets = <&rstgen JH7100_RSTN_USB_AXI>, + <&rstgen JH7100_RSTN_USBNOC_AXI>; + reset-names = "axi", "nocaxi"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x00000 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <44>, <52>, <43>; + interrupt-names = "host", "peripheral", "otg"; + }; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; |