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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2023-02-14 00:51:10 +0300
committerAnup Patel <anup@brainfault.org>2023-02-27 09:06:06 +0300
commit2491242282b4e3bb0617f41dfb667ca9a8241c0a (patch)
tree83059e1648aa910c52ba3dcec9b20437ed1a8b87
parentc10095132aca1711a485fb25865237e0e768341c (diff)
downloadopensbi-2491242282b4e3bb0617f41dfb667ca9a8241c0a.tar.xz
platform: generic: renesas: rzfive: Configure the PMA region
On the Renesas RZ/Five SoC by default we want to configure 128MiB of memory ranging from 0x58000000 as a non-cacheable + bufferable region in the PMA and populate this region as PMA reserve DT node with shared DMA pool and no-map flags set so that Linux drivers requesting any DMA'able memory go through this region. PMA node passed to the above stack: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
-rw-r--r--platform/generic/Kconfig1
-rw-r--r--platform/generic/renesas/rzfive/rzfive.c21
2 files changed, 22 insertions, 0 deletions
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 39fb4e9..1f4f8e1 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -35,6 +35,7 @@ config PLATFORM_ANDES_AE350
config PLATFORM_RENESAS_RZFIVE
bool "Renesas RZ/Five support"
+ select ANDES45_PMA
default n
config PLATFORM_SIFIVE_FU540
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index ee9c9c4..4d71d0d 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -4,10 +4,30 @@
*
*/
+#include <andes/andes45_pma.h>
#include <platform_override.h>
#include <sbi/sbi_domain.h>
#include <sbi_utils/fdt/fdt_helper.h>
+static const struct andes45_pma_region renesas_rzfive_pma_regions[] = {
+ {
+ .pa = 0x58000000,
+ .size = 0x8000000,
+ .flags = ANDES45_PMACFG_ETYP_NAPOT |
+ ANDES45_PMACFG_MTYP_MEM_NON_CACHE_BUF,
+ .dt_populate = true,
+ .shared_dma = true,
+ .no_map = true,
+ .dma_default = true,
+ },
+};
+
+static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *match)
+{
+ return andes45_pma_setup_regions(renesas_rzfive_pma_regions,
+ array_size(renesas_rzfive_pma_regions));
+}
+
int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
{
/*
@@ -34,4 +54,5 @@ static const struct fdt_match renesas_rzfive_match[] = {
const struct platform_override renesas_rzfive = {
.match_table = renesas_rzfive_match,
.early_init = renesas_rzfive_early_init,
+ .final_init = renesas_rzfive_final_init,
};