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| author | Samuel Holland <samuel@sholland.org> | 2021-10-18 08:33:50 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-10-21 07:36:00 +0300 |
| commit | 78c2b19218bd62653b9fb31623a42ced45f38ea6 (patch) | |
| tree | cacc2885adb9fdb6aa7706a738b20e14b25956b9 /docs | |
| parent | 422eda499cd6b69c0ca9f4cb06b3aceef17a3b27 (diff) | |
| download | opensbi-78c2b19218bd62653b9fb31623a42ced45f38ea6.tar.xz | |
lib: utils/irqchip: Automatically delegate T-HEAD PLIC accessOpenSBI-v0.9-78c2b19
The T-HEAD PLIC implementation requires setting a delegation bit
to allow access from S-mode. Now that the T-HEAD PLIC has its own
compatible string, set this bit automatically from the PLIC driver,
instead of reaching into the PLIC's MMIO space from another driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/platform/thead-c9xx.md | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/docs/platform/thead-c9xx.md b/docs/platform/thead-c9xx.md index c0daeb7..3490ed5 100644 --- a/docs/platform/thead-c9xx.md +++ b/docs/platform/thead-c9xx.md @@ -51,11 +51,6 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906) compatible = "simple-bus"; ranges; - reset: reset-sample { - compatible = "thead,reset-sample"; - plic-delegate = <0x0 0x101ffffc>; - }; - clint0: clint@14000000 { compatible = "riscv,clint0"; interrupts-extended = < @@ -67,7 +62,8 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906) intc: interrupt-controller@10000000 { #interrupt-cells = <1>; - compatible = "riscv,plic0"; + compatible = "allwinner,sun20i-d1-plic", + "thead,c900-plic"; interrupt-controller; interrupts-extended = < &cpu0_intc 0xffffffff &cpu0_intc 9 @@ -150,7 +146,6 @@ DTS Example2: (Multi cores with soc reset-regs) reset: reset-sample { compatible = "thead,reset-sample"; - plic-delegate = <0xff 0xd81ffffc>; entry-reg = <0xff 0xff019050>; entry-cnt = <4>; control-reg = <0xff 0xff015004>; @@ -173,7 +168,7 @@ DTS Example2: (Multi cores with soc reset-regs) intc: interrupt-controller@ffd8000000 { #interrupt-cells = <1>; - compatible = "riscv,plic0"; + compatible = "thead,c900-plic"; interrupt-controller; interrupts-extended = < &cpu0_intc 0xffffffff &cpu0_intc 9 @@ -194,7 +189,6 @@ DTS Example2: (Multi cores with old reset csrs) ``` reset: reset-sample { compatible = "thead,reset-sample"; - plic-delegate = <0xff 0xd81ffffc>; using-csr-reset; csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x3b0 0x3b1 0x3b2 0x3b3 |