diff options
| author | Xiang W <wxjstz@126.com> | 2021-03-30 15:07:35 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-04-01 08:18:35 +0300 |
| commit | 4ef2f5d3e6b25356a8fab19574bed76ce60edeee (patch) | |
| tree | 3b00b17d3ef93d4b8bb968f151810d179d0cb2ba /firmware | |
| parent | 4edc8224073e61498b1de338c67174f47fc3c5e1 (diff) | |
| download | opensbi-4ef2f5d3e6b25356a8fab19574bed76ce60edeee.tar.xz | |
firware: optimize the exception exit code
There are two copies of the same abnormal exit code, this patch deletes one
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/fw_base.S | 24 |
1 files changed, 2 insertions, 22 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index 2ce3851..c897ed0 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -711,6 +711,7 @@ fw_platform_init: .section .entry, "ax", %progbits .align 3 .globl _trap_handler + .globl _trap_exit _trap_handler: TRAP_SAVE_AND_SETUP_SP_T0 @@ -720,17 +721,6 @@ _trap_handler: TRAP_CALL_C_ROUTINE - TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0 - - TRAP_RESTORE_MEPC_MSTATUS 0 - - TRAP_RESTORE_SP_T0 - - mret - - .section .entry, "ax", %progbits - .align 3 - .globl _trap_exit _trap_exit: add sp, a0, zero @@ -746,6 +736,7 @@ _trap_exit: .section .entry, "ax", %progbits .align 3 .globl _trap_handler_rv32_hyp + .globl _trap_exit_rv32_hyp _trap_handler_rv32_hyp: TRAP_SAVE_AND_SETUP_SP_T0 @@ -755,17 +746,6 @@ _trap_handler_rv32_hyp: TRAP_CALL_C_ROUTINE - TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0 - - TRAP_RESTORE_MEPC_MSTATUS 1 - - TRAP_RESTORE_SP_T0 - - mret - - .section .entry, "ax", %progbits - .align 3 - .globl _trap_exit_rv32_hyp _trap_exit_rv32_hyp: add sp, a0, zero |