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| author | Nylon Chen <nylon.chen@sifive.com> | 2023-02-10 11:52:38 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-02-27 08:52:11 +0300 |
| commit | 30ea8069f4c704e67017215f90f74b8588ee9bdf (patch) | |
| tree | 389237de2dabdc8e54ab040c039b76846fa6fbb1 /include | |
| parent | 4f2be401025d7f5095dd2a4d2acad0fa60ef15e0 (diff) | |
| download | opensbi-30ea8069f4c704e67017215f90f74b8588ee9bdf.tar.xz | |
lib: sbi_hart: Enable hcontext and scontext
According to the description in "riscv-state-enable[0]", to access
h/scontext in S-Mode, we need to enable the 57th bit.
If it is not enabled, an "illegal instruction" error will occur.
Link: https://github.com/riscv/riscv-state-enable/blob/a28bfae443f350d5b4c42874f428367d5b322ffe/content.adoc [0]
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index b0f08c8..4ebed97 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -736,6 +736,8 @@ #define SMSTATEEN0_CS (_ULL(1) << SMSTATEEN0_CS_SHIFT) #define SMSTATEEN0_FCSR_SHIFT 1 #define SMSTATEEN0_FCSR (_ULL(1) << SMSTATEEN0_FCSR_SHIFT) +#define SMSTATEEN0_CONTEXT_SHIFT 57 +#define SMSTATEEN0_CONTEXT (_ULL(1) << SMSTATEEN0_CONTEXT_SHIFT) #define SMSTATEEN0_IMSIC_SHIFT 58 #define SMSTATEEN0_IMSIC (_ULL(1) << SMSTATEEN0_IMSIC_SHIFT) #define SMSTATEEN0_AIA_SHIFT 59 |