diff options
| author | minda.chen <minda.chen@starfivetech.com> | 2022-12-14 09:15:50 +0300 |
|---|---|---|
| committer | minda.chen <minda.chen@starfivetech.com> | 2023-01-03 09:13:57 +0300 |
| commit | 097a45c6a905310307c3052012d44098c0e3f30f (patch) | |
| tree | 709665a35393479cbb65ba66fb4f40fb4ce94a15 /arch | |
| parent | 8a4e190ee227330d340324ea4c4277c702f2ae9b (diff) | |
| download | u-boot-097a45c6a905310307c3052012d44098c0e3f30f.tar.xz | |
dts: pmu : add riscv pmu dts config
add 7110 performance monitor for perf use
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 0188f89780..53d3953bc3 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -164,6 +164,52 @@ #clock-cells = <1>; ranges; + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = <0x5 0x06 0x18 + 0x08 0x09 0x18>; + riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000 + 0x06 0x00000000 0x4001 + 0x08 0x00000000 0x4008 + 0x09 0x00000000 0x4009>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x100 0xffffffff 0xffffffff 0x18 + 0x00000000 0x200 0xffffffff 0xffffffff 0x18 + 0x00000000 0x400 0xffffffff 0xffffffff 0x18 + 0x00000000 0x800 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x4000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x8000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x10000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x20000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x40000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x80000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x100000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x200000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x400000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x800000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1000000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2000000 0xffffffff 0xffffffff 0x18 + 0x00000000 0x101 0xffffffff 0xffffffff 0x18 + 0x00000000 0x201 0xffffffff 0xffffffff 0x18 + 0x00000000 0x401 0xffffffff 0xffffffff 0x18 + 0x00000000 0x801 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x4001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x8001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x10001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x20001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x40001 0xffffffff 0xffffffff 0x18 + 0x00000000 0x102 0xffffffff 0xffffffff 0x18 + 0x00000000 0x202 0xffffffff 0xffffffff 0x18 + 0x00000000 0x402 0xffffffff 0xffffffff 0x18 + 0x00000000 0x802 0xffffffff 0xffffffff 0x18 + 0x00000000 0x1002 0xffffffff 0xffffffff 0x18 + 0x00000000 0x2002 0xffffffff 0xffffffff 0x18>; + }; + cachectrl: cache-controller@2010000 { compatible = "sifive,fu740-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>; |