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| author | Minda Chen <minda.chen@starfivetech.com> | 2023-08-25 11:16:19 +0300 |
|---|---|---|
| committer | Minda Chen <minda.chen@starfivetech.com> | 2023-08-25 11:18:51 +0300 |
| commit | 37cf2331abec749f33deaefe30c31d266b62d076 (patch) | |
| tree | f06c72ec4261eee32951e4a38c7239d94f720151 /arch | |
| parent | f64678cdc6e51d09c9a7de1a04c011a6be8eec27 (diff) | |
| download | u-boot-37cf2331abec749f33deaefe30c31d266b62d076.tar.xz | |
dts: usb: Add USB 3.0 clock dts.
Add evb USB 3.0 clock dts.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/dts/starfive_evb.dts | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts index 19b8e5f1e0..0ce86ad8bd 100644 --- a/arch/riscv/dts/starfive_evb.dts +++ b/arch/riscv/dts/starfive_evb.dts @@ -297,6 +297,21 @@ }; &usbdrd30 { + clocks = <&clkgen JH7110_USB_125M>, + <&clkgen JH7110_USB0_CLK_APP_125>, + <&clkgen JH7110_USB0_CLK_LPM>, + <&clkgen JH7110_USB0_CLK_STB>, + <&clkgen JH7110_USB0_CLK_USB_APB>, + <&clkgen JH7110_USB0_CLK_AXI>, + <&clkgen JH7110_USB0_CLK_UTMI_APB>, + <&clkgen JH7110_PCIE0_CLK_APB>; + clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy"; + resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>, + <&rstgen RSTN_U0_CDN_USB_APB>, + <&rstgen RSTN_U0_CDN_USB_AXI>, + <&rstgen RSTN_U0_CDN_USB_UTMI_APB>, + <&rstgen RSTN_U0_PLDA_PCIE_APB>; + reset-names = "pwrup","apb","axi","utmi", "phy"; status = "okay"; }; |