clk:starfive: Add vout clock driver for StarFive JH7110

Add vout clock driver for StarFive JH7110

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>

2 files changed, 57 insertions, 66 deletions

diff --git a/include/dt-bindings/clock/starfive-jh7110-clkgen.h b/include/dt-bindings/clock/starfive-jh7110-clkgen.h
index 1228a8c94b..c2df56f222 100644
--- a/include/dt-bindings/clock/starfive-jh7110-clkgen.h
+++ b/include/dt-bindings/clock/starfive-jh7110-clkgen.h
@@ -391,4 +391,61 @@
 #define JH7110_GMAC0_RGMII_RXIN         (JH7110_CLK_END + 13)
 #define JH7110_CLK_RTC                  (JH7110_CLK_END + 14)
 
+#define JH7110_CLK_VOUT_START				(JH7110_CLK_RTC + 1)
+
+/* vout regisger */
+#define JH7110_APB					(JH7110_CLK_VOUT_START + 0)
+#define JH7110_DC8200_PIX0				(JH7110_CLK_VOUT_START + 1)
+#define JH7110_DSI_SYS					(JH7110_CLK_VOUT_START + 2)
+#define JH7110_TX_ESC					(JH7110_CLK_VOUT_START + 3)
+#define JH7110_U0_DC8200_CLK_AXI			(JH7110_CLK_VOUT_START + 4)
+#define JH7110_U0_DC8200_CLK_CORE			(JH7110_CLK_VOUT_START + 5)
+#define JH7110_U0_DC8200_CLK_AHB			(JH7110_CLK_VOUT_START + 6)
+#define JH7110_U0_DC8200_CLK_PIX0			(JH7110_CLK_VOUT_START + 7)
+#define JH7110_U0_DC8200_CLK_PIX1			(JH7110_CLK_VOUT_START + 8)
+#define JH7110_DOM_VOUT_TOP_LCD_CLK			(JH7110_CLK_VOUT_START + 9)
+#define JH7110_U0_CDNS_DSITX_CLK_APB			(JH7110_CLK_VOUT_START + 10)
+#define JH7110_U0_CDNS_DSITX_CLK_SYS			(JH7110_CLK_VOUT_START + 11)
+#define JH7110_U0_CDNS_DSITX_CLK_DPI			(JH7110_CLK_VOUT_START + 12)
+#define JH7110_U0_CDNS_DSITX_CLK_TXESC			(JH7110_CLK_VOUT_START + 13)
+#define JH7110_U0_MIPITX_DPHY_CLK_TXESC		(JH7110_CLK_VOUT_START + 14)
+#define JH7110_U0_HDMI_TX_CLK_MCLK			(JH7110_CLK_VOUT_START + 15)
+#define JH7110_U0_HDMI_TX_CLK_BCLK			(JH7110_CLK_VOUT_START + 16)
+#define JH7110_U0_HDMI_TX_CLK_SYS			(JH7110_CLK_VOUT_START + 17)
+
+#define JH7110_CLK_VOUT_REG_END			(JH7110_CLK_VOUT_START + 18)
+
+/* vout other */
+#define JH7110_DISP_ROOT				(JH7110_CLK_VOUT_START + 18)
+#define JH7110_DISP_AXI				(JH7110_CLK_VOUT_START + 19)
+#define JH7110_DISP_AHB				(JH7110_CLK_VOUT_START + 20)
+#define JH7110_HDMI_PHY_REF				(JH7110_CLK_VOUT_START + 21)
+#define JH7110_HDMITX0_MCLK				(JH7110_CLK_VOUT_START + 22)
+#define JH7110_HDMITX0_SCK				(JH7110_CLK_VOUT_START + 23)
+
+#define JH7110_MIPI_DPHY_REF				(JH7110_CLK_VOUT_START + 24)
+#define JH7110_U0_PCLK_MUX_BIST_PCLK			(JH7110_CLK_VOUT_START + 25)
+#define JH7110_DISP_APB				(JH7110_CLK_VOUT_START + 26)
+#define JH7110_U0_PCLK_MUX_FUNC_PCLK			(JH7110_CLK_VOUT_START + 27)
+#define JH7110_U0_DOM_VOUT_CRG_PCLK			(JH7110_CLK_VOUT_START + 28)
+#define JH7110_U0_DOM_VOUT_SYSCON_PCLK			(JH7110_CLK_VOUT_START + 29)
+#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB	(JH7110_CLK_VOUT_START + 30)
+#define JH7110_U0_AHB2APB_CLK_AHB			(JH7110_CLK_VOUT_START + 31)
+#define JH7110_U0_P2P_ASYNC_CLK_APBS			(JH7110_CLK_VOUT_START + 32)
+#define JH7110_U0_CDNS_DSITX_CLK_RXESC			(JH7110_CLK_VOUT_START + 33)
+#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS		(JH7110_CLK_VOUT_START + 34)
+#define JH7110_U0_MIPITX_DPHY_CLK_SYS			(JH7110_CLK_VOUT_START + 35)
+#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF		(JH7110_CLK_VOUT_START + 36)
+#define JH7110_U0_MIPITX_APBIF_PCLK			(JH7110_CLK_VOUT_START + 37)
+#define JH7110_HDMI_TX_CLK_REF				(JH7110_CLK_VOUT_START + 38)
+#define JH7110_U0_DC8200_CLK_PIX0_OUT			(JH7110_CLK_VOUT_START + 39)
+#define JH7110_U0_DC8200_CLK_PIX1_OUT			(JH7110_CLK_VOUT_START + 40)
+
+#define JH7110_CLK_VOUT_END				(JH7110_CLK_VOUT_START + 41)
+
+/* vout external clocks */
+#define JH7110_HDMITX0_PIXELCLK		(JH7110_CLK_VOUT_END + 0)
+#define JH7110_MIPITX_DPHY_RXESC		(JH7110_CLK_VOUT_END + 1)
+#define JH7110_MIPITX_DPHY_TXBYTEHS		(JH7110_CLK_VOUT_END + 2)
+
 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
diff --git a/include/dt-bindings/clock/starfive-jh7110-vout.h b/include/dt-bindings/clock/starfive-jh7110-vout.h
deleted file mode 100644
index e76a80a5f1..0000000000
--- a/include/dt-bindings/clock/starfive-jh7110-vout.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/*
- * Copyright 2022 StarFive, Inc <xingyu.wu@starfivetech.com>
- */
-
-#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__
-#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__
-
-/* regisger */
-#define JH7110_APB						0
-#define JH7110_DC8200_PIX0					1
-#define JH7110_DSI_SYS						2
-#define JH7110_TX_ESC						3
-#define JH7110_U0_DC8200_CLK_AXI				4
-#define JH7110_U0_DC8200_CLK_CORE				5
-#define JH7110_U0_DC8200_CLK_AHB				6
-#define JH7110_U0_DC8200_CLK_PIX0				7
-#define JH7110_U0_DC8200_CLK_PIX1				8
-#define JH7110_DOM_VOUT_TOP_LCD_CLK				9
-#define JH7110_U0_CDNS_DSITX_CLK_APB				10
-#define JH7110_U0_CDNS_DSITX_CLK_SYS				11
-#define JH7110_U0_CDNS_DSITX_CLK_DPI				12
-#define JH7110_U0_CDNS_DSITX_CLK_TXESC				13
-#define JH7110_U0_MIPITX_DPHY_CLK_TXESC				14
-#define JH7110_U0_HDMI_TX_CLK_MCLK				15
-#define JH7110_U0_HDMI_TX_CLK_BCLK				16
-#define JH7110_U0_HDMI_TX_CLK_SYS				17
-
-#define JH7110_CLK_VOUT_REG_END					18
-
-/* other */
-#define JH7110_DISP_ROOT					18
-#define JH7110_DISP_AXI						19
-#define JH7110_DISP_AHB						20
-#define JH7110_HDMI_PHY_REF					21
-#define JH7110_HDMITX0_MCLK					22
-#define JH7110_HDMITX0_SCK					23
-
-#define JH7110_MIPI_DPHY_REF					24
-#define JH7110_U0_PCLK_MUX_BIST_PCLK				25
-#define JH7110_DISP_APB						26
-#define JH7110_U0_PCLK_MUX_FUNC_PCLK				27
-#define JH7110_U0_DOM_VOUT_CRG_PCLK				28
-#define JH7110_U0_DOM_VOUT_SYSCON_PCLK				29
-#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB		30
-#define JH7110_U0_AHB2APB_CLK_AHB				31
-#define JH7110_U0_P2P_ASYNC_CLK_APBS				32
-#define JH7110_U0_CDNS_DSITX_CLK_RXESC				33
-#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS			34
-#define JH7110_U0_MIPITX_DPHY_CLK_SYS				35
-#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF			36
-#define JH7110_U0_MIPITX_APBIF_PCLK				37
-#define JH7110_HDMI_TX_CLK_REF					38
-#define JH7110_U0_DC8200_CLK_PIX0_OUT				39
-#define JH7110_U0_DC8200_CLK_PIX1_OUT				40
-
-#define JH7110_CLK_VOUT_END					41
-
-/* external clocks */
-#define JH7110_HDMITX0_PIXELCLK			(JH7110_CLK_VOUT_END + 0)
-#define JH7110_MIPITX_DPHY_RXESC		(JH7110_CLK_VOUT_END + 1)
-#define JH7110_MIPITX_DPHY_TXBYTEHS		(JH7110_CLK_VOUT_END + 2)
-
-
-
-#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */