starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-03-08	arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64	Siew Chin Lim	1	-1/+1
2021-02-23	Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodia...	Tom Rini	1	-1/+1
2021-02-23	fpga: zynqpl: fix buffer alignment	Michael Walle	1	-1/+1
2021-02-16	image: Adjust the workings of fit_check_format()	Simon Glass	1	-3/+3
2021-02-02	common: Drop asm/global_data.h from common header	Simon Glass	2	-0/+2
2021-01-15	arm: socfpga: soc64: Add ATF support for FPGA reconfig driver	Chee Hong Ang	1	-0/+139
2020-10-09	arm: socfpga: agilex: Enable FPGA Full Reconfiguration support	Chee Hong Ang	1	-1/+1
2020-10-09	fpga: intel_sdm_mb: Add watchdog reset	Chee Hong Ang	1	-0/+3
2020-10-09	fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox	Chee Hong Ang	4	-11/+12
2020-09-23	fpga: zynqmp: Protect zynqmp_loads() for SPL	Michal Simek	1	-1/+1
2020-09-23	fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macros	Michal Simek	1	-4/+4
2020-08-20	xilinx: zynqmp: synchronize firmware call return payload	Ibai Erkiaga	1	-1/+1
2020-08-04	fs: fs-loader: Drop dm.h header file	Simon Glass	1	-0/+1
2020-06-24	arm64: xilinx: Print fpga error value in hex	T Karthik Reddy	2	-2/+2
2020-06-24	fpga: zynqpl: Flush dcache only for non-bitstream data	T Karthik Reddy	1	-2/+3
2020-06-24	fpga: zynqpl: Check if aes engine is enabled	Ibai Erkiaga	1	-0/+8
2020-06-24	fpga: zynqpl: Check fpga config completion	T Karthik Reddy	1	-2/+17
2020-06-24	fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes	Siva Durga Prasad Paladugu	1	-3/+4
2020-05-19	common: Drop linux/bitops.h from common header	Simon Glass	2	-0/+2
2020-05-19	common: Drop linux/delay.h from common header	Simon Glass	9	-0/+9
2020-05-19	Fix some checkpatch warnings in calls to udelay()	Simon Glass	1	-3/+3
2020-05-19	common: Drop log.h from common header	Simon Glass	11	-0/+11
2020-05-19	common: Drop init.h from common header	Simon Glass	1	-0/+1
2020-05-19	common: Drop image.h from common header	Simon Glass	1	-0/+1
2020-05-19	common: Drop net.h from common header	Simon Glass	3	-0/+3
2020-02-06	dm: core: Create a new header file for 'compat' features	Simon Glass	1	-0/+1
2020-01-07	arm: socfpga: Convert system manager from struct to defines	Ley Foon Tan	2	-8/+3
2019-12-03	common: Move ARM cache operations out of common.h	Simon Glass	2	-0/+2
2019-12-03	common: Move some cache and MMU functions out of common.h	Simon Glass	1	-0/+1
2019-10-24	arm64: zynqmp: Convert invoke_smc() to xilinx_pm_request()	Michal Simek	1	-7/+9
2019-10-24	arm64: versal: Rename versal_pm_request to xilinx_pm_request	Michal Simek	1	-1/+1
2019-10-24	arm64: xilinx: Move firmware functions from platform to driver	Michal Simek	1	-0/+1
2019-10-08	arm64: zynqmp: use firmware driver to get version	Ibai Erkiaga	1	-2/+2
2019-10-08	firmware: zynqmp: create firmware header	Ibai Erkiaga	1	-0/+1
2019-10-08	fpga: zynqmp: Fix second local variable declaration	Michal Simek	1	-1/+1
2019-10-08	arm64: versal: fpga: Add PL bit stream load support	Siva Durga Prasad Paladugu	4	-1/+68
2019-07-30	fpga: altera: cyclon2: Check function pointer before calling	Alexander Dahl	1	-1/+5
2019-07-30	fpga: altera: cyclon2: Fix indentation	Alexander Dahl	1	-16/+16
2019-07-30	fpga: altera: cyclon2: Fix most checkpatch warnings	Alexander Dahl	1	-42/+39
2019-07-30	fpga: virtex2: Add slave serial programming support	Robert Hancock	1	-13/+83
2019-07-30	fpga: virtex2: Add additional clock cycles after DONE assertion	Robert Hancock	1	-4/+16
2019-07-30	fpga: virtex2: Split out image writing from pre/post operations	Robert Hancock	1	-157/+174
2019-07-30	fpga: virtex2: added Kconfig option	Robert Hancock	1	-0/+8
2019-07-30	fpga: virtex2: cosmetic: Cleanup code style	Robert Hancock	1	-134/+136
2019-07-21	fpga: arria10: Fix error in fpga pin configuration	Dalon Westergreen	1	-4/+5
2019-05-10	spl: socfpga: Implement fpga bitstream loading with socfpga loadfs	Tien Fong Chee	1	-1/+1
2019-05-10	ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading	Tien Fong Chee	1	-13/+484
2019-05-10	ARM: socfpga: Moving the watchdog reset to the for-loop status polling	Tien Fong Chee	1	-1/+1
2019-05-10	ARM: socfpga: Cleaning up and ensuring consistent format messages in driver	Tien Fong Chee	1	-6/+7
2019-04-16	arm: zynq: Add an info message about post config	Siva Durga Prasad Paladugu	1	-0/+2