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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
* Author: yanhong <yanhong.wang@starfivetech.com>
*
*/
#ifndef __STARFIVE_JH7110_REGS_H
#define __STARFIVE_JH7110_REGS_H
/*system control register*/
#define STG_SYSCON_BASE 0x10240000
#define SYS_SYSCON_BASE 0x13030000
#define SYS_IOMUX_BASE 0x13040000
#define AON_SYSCON_BASE 0x17010000
#define SYS_CRG_BASE 0x13020000
#define AON_CRG_BASE 0x17000000
#define AON_IOMUX_BASE 0x17020000
#define STG_CRG_BASE 0x10230000
#define CLK_ENABLE_MASK 0x80000000U
#define SYS_CRG_RESET_ASSERT3_SHIFT 0X304U
#define SYS_CRG_RESET_STATUS3_SHIFT 0X314U
/*gmac cfg*/
#define AON_SYSCFG_12 0xCU
#define SYS_SYSCON_144 0x90U
#define GMAC5_0_SEL_I_SHIFT 0x12U
#define GMAC5_0_SEL_I_MASK 0x1C0000U
#define GMAC5_0_CLK_TX_SHIFT 0x14
#define GMAC5_0_CLK_RX_SHIFT 0x1C
#define GMAC5_0_CLK_TX_BIT 0x18
#define GMAC5_0_CLK_TX_MASK 0x1000000U
#define GMAC5_1_SEL_I_SHIFT 0x2U
#define GMAC5_1_SEL_I_MASK 0x1CU
#define GMAC5_1_CLK_TX_SHIFT 0x1A4
#define GMAC5_1_CLK_RX_SHIFT 0x19C
#define GMAC5_1_CLK_TX_BIT 0x18
#define GMAC5_1_CLK_TX_MASK 0x1000000U
/*usb cfg*/
#define STG_SYSCON_4 0x4U
#define STG_SYSCON_196 0xC4U
#define STG_SYSCON_328 0x148U
#define STG_SYSCON_500 0x1F4U
#define SYS_SYSCON_24 0x18U
#define SYS_SYSCON_28 0x1CU
#define SYS_SYSCON_32 0x20U
#define SYS_SYSCON_36 0x24U
#define SYS_IOMUX_32 0x80U
#define USB_MODE_STRAP_SHIFT 0x10U
#define USB_MODE_STRAP_MASK 0x70000U
#define USB_OTG_SUSPENDM_BYPS_SHIFT 0x14U
#define USB_OTG_SUSPENDM_BYPS_MASK 0x100000U
#define USB_OTG_SUSPENDM_SHIFT 0x13U
#define USB_OTG_SUSPENDM_MASK 0x80000U
#define USB_PLL_EN_SHIFT 0x16U
#define USB_PLL_EN_MASK 0x400000U
#define USB_REFCLK_MODE_SHIFT 0x17U
#define USB_REFCLK_MODE_MASK 0x800000U
#define PDRSTN_SPLIT_SHIFT 0x11U
#define PDRSTN_SPLIT_MASK 0x20000U
#define IOMUX_USB_SHIFT 0x10U
#define IOMUX_USB_MASK 0x7F0000U
#define PCIE_CKREF_SRC_SHIFT 0x12U
#define PCIE_CKREF_SRC_MASK 0xC0000U
#define PCIE_CLK_SEL_SHIFT 0x14U
#define PCIE_CLK_SEL_MASK 0x300000U
#define PCIE_PHY_MODE_SHIFT 0x14U
#define PCIE_PHY_MODE_MASK 0x300000U
#define PCIE_USB3_BUS_WIDTH_SHIFT 0x2U
#define PCIE_USB3_BUS_WIDTH_MASK 0xCU
#define PCIE_USB3_RATE_SHIFT 0x5U
#define PCIE_USB3_RATE_MASK 0x60U
#define PCIE_USB3_RX_STANDBY_SHIFT 0x7U
#define PCIE_USB3_RX_STANDBY_MASK 0x80U
#define PCIE_USB3_PHY_ENABLE_SHIFT 0x4U
#define PCIE_USB3_PHY_ENABLE_MASK 0x10U
#define AON_GPIO_DIN_REG 0x2c
/*timer cfg*/
#define TIMER_CLK_APB_SHIFT 0x1F0U
#define TIMER_CLK_TIMER0_SHIFT 0x1F4U
#define TIMER_CLK_TIMER1_SHIFT 0x1F8U
#define TIMER_CLK_TIMER2_SHIFT 0x1FCU
#define TIMER_CLK_TIMER3_SHIFT 0x200U
#define TIMER_RSTN_APB_SHIFT 21
#define TIMER_RSTN_TIMER0_SHIFT 22
#define TIMER_RSTN_TIMER1_SHIFT 23
#define TIMER_RSTN_TIMER2_SHIFT 24
#define TIMER_RSTN_TIMER3_SHIFT 25
#define CLK_CPU_ROOT_OFFSET 0x0
#define CLK_CPU_ROOT_SW_SHIFT 24
#define CLK_CPU_ROOT_SW_MASK 0x1000000U
#define CLK_PERH_ROOT_OFFSET 0x10
#define CLK_PERH_ROOT_SHIFT 24
#define CLK_PERH_ROOT_MASK 0x1000000U
#define CLK_BUS_ROOT_OFFSET 0x14
#define CLK_BUS_ROOT_SW_SHIFT 24
#define CLK_BUS_ROOT_SW_MASK 0x1000000U
#define CLK_NOC_BUS_STG_AXI_OFFSET 0x180
#define CLK_NOC_BUS_STG_AXI_EN_SHIFT 31
#define CLK_NOC_BUS_STG_AXI_EN_MASK 0x80000000U
#define CLK_AON_APB_FUNC_OFFSET 0x4
#define CLK_AON_APB_FUNC_SW_SHIFT 24
#define CLK_AON_APB_FUNC_SW_MASK 0x1000000U
#define CLK_QSPI_REF_OFFSET 0x168
#define CLK_QSPI_REF_SW_SHIFT 24
#define CLK_QSPI_REF_SW_MASK 0x1000000U
#define CLK_UART2_APB_OFFSET 0x254
#define CLK_UART2_CORE_OFFSET 0x258
#define CLK_RSTN_3_OFFSET 0x300
#endif /* __STARFIVE_JH7110_REGS_H */
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