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author | Mark Brown <broonie@kernel.org> | 2021-09-20 17:56:58 +0300 |
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committer | Mark Brown <broonie@kernel.org> | 2021-09-21 17:23:35 +0300 |
commit | ffb1e76f4f32d2b8ea4189df0484980370476395 (patch) | |
tree | c62376eab558809973dc5b71806df07c388bfc1a /Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | |
parent | 2bab94090b01bc593d8bc25f68df41f198721173 (diff) | |
parent | e4e737bb5c170df6135a127739a9e6148ee3da82 (diff) | |
download | linux-ffb1e76f4f32d2b8ea4189df0484980370476395.tar.xz |
Merge tag 'v5.15-rc2' into spi-5.15
Linux 5.15-rc2
Diffstat (limited to 'Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 5272b6f284ba..dcd63908aeae 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -77,6 +77,34 @@ properties: Type-C spec states minimum CC pin debounce of 100 ms and maximum of 200 ms. However, some solutions might need more than 200 ms. + refclk-dig: + type: object + description: | + WIZ node should have subnode for refclk_dig to select the reference + clock source for the reference clock used in the PHY and PMA digital + logic. + properties: + clocks: + minItems: 2 + maxItems: 4 + description: Phandle to two (Torrent) or four (Sierra) clock nodes representing + the inputs to refclk_dig + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + patternProperties: "^pll[0|1]-refclk$": type: object @@ -121,34 +149,6 @@ patternProperties: - clocks - "#clock-cells" - "^refclk-dig$": - type: object - description: | - WIZ node should have subnode for refclk_dig to select the reference - clock source for the reference clock used in the PHY and PMA digital - logic. - properties: - clocks: - minItems: 2 - maxItems: 4 - description: Phandle to two (Torrent) or four (Sierra) clock nodes representing - the inputs to refclk_dig - - "#clock-cells": - const: 0 - - assigned-clocks: - maxItems: 1 - - assigned-clock-parents: - maxItems: 1 - - required: - - clocks - - "#clock-cells" - - assigned-clocks - - assigned-clock-parents - "^serdes@[0-9a-f]+$": type: object description: | |