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authorNikolay Borisov <nborisov@suse.com>2018-02-21 02:25:08 +0300
committerIngo Molnar <mingo@kernel.org>2018-02-21 11:58:14 +0300
commit51de78892b1294d1521c41226a5ef215a910c25f (patch)
treed19d3b72ed13ab8ce1a7429b792d4424135c2b32 /Documentation/memory-barriers.txt
parent621df431b0ac931e318679f54047c47eb23cfdd2 (diff)
downloadlinux-51de78892b1294d1521c41226a5ef215a910c25f.tar.xz
memory-barriers: Fix description of data dependency barriers
In the description of data dependency barriers the words 'before' is used erroneously. Since such barrier order dependent loads one after the other. So substitute 'before' with 'after'. Signed-off-by: Nikolay Borisov <nborisov@suse.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: akiyks@gmail.com Cc: boqun.feng@gmail.com Cc: dhowells@redhat.com Cc: j.alglave@ucl.ac.uk Cc: linux-arch@vger.kernel.org Cc: luc.maranget@inria.fr Cc: npiggin@gmail.com Cc: parri.andrea@gmail.com Cc: stern@rowland.harvard.edu Cc: will.deacon@arm.com Link: http://lkml.kernel.org/r/1519169112-20593-8-git-send-email-paulmck@linux.vnet.ibm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'Documentation/memory-barriers.txt')
-rw-r--r--Documentation/memory-barriers.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index a37d3aff3e73..da6525bdc3f5 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -403,7 +403,7 @@ Memory barriers come in four basic varieties:
where two loads are performed such that the second depends on the result
of the first (eg: the first load retrieves the address to which the second
load will be directed), a data dependency barrier would be required to
- make sure that the target of the second load is updated before the address
+ make sure that the target of the second load is updated after the address
obtained by the first load is accessed.
A data dependency barrier is a partial ordering on interdependent loads