i3c: dw: master: flexible I3C timing control

Enabling mechanism which allows user to control I3C timings
with details. It is done over DT. The following options are possible:
* 'i3c-od-scl-low-ns' - to control SCL low period I3C Open Drain mode,
                      example: i3c-od-scl-low-ns = <250>;
* 'i3c-od-scl-high-ns' - to control SCL high period I3C Open Drain mode,
                      example: i3c-od-scl-high-ns = <40>;
* 'i3c-pp-scl-low-ns' - to control SCL low period I3C Push-Pull mode,
                      example: i3c-pp-scl-low-ns = <100>;
* 'i3c-pp-scl-high-ns' - to control SCL high period I3C Push-Pull mode,
                      example: i3c-pp-scl-low-ns = <200>;
* 'sda-tx-hold-ns' - to control hold time of the transmit data (SDA)
                     with respect to the SCL edge,
                     example: sda-tx-hold-ns = <15>;
All values shall be provided in nanoseconds.
Driver does necessary validation against limits documented in I3C MIPI
specification. Driver also does the calculation in case only low, only
high period or none of them are provided. DT SCL clock value parameters
('i2c-scl-hz', 'i3c-scl-hz') are also taken into account during the
calculation.
For instance if user provides 'i3c-od-scl-low-ns' and 'i2c-scl-hz',
driver calculates SCL high period or reports an error if it is not
possible.
If user provides only 'i2c-scl-hz', driver calculates SCL low and high
periods.
If user provides all of these parameters, driver does the validation
and reports an error in case parameters values does not match.

Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>

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