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authorGabriel Fernandez <gabriel.fernandez@st.com>2019-02-14 13:40:47 +0300
committerStephen Boyd <sboyd@kernel.org>2019-02-22 01:13:22 +0300
commit97621d22df60d7348826d2e4b0c349673faeb4b8 (patch)
treeac29bc3ffd9de2b4cf44f8b87dfc423529204091 /drivers/clk/clk-stm32mp1.c
parentf9b76fd24d0a0cd7b3d9309b93c36c9c32526b00 (diff)
downloadlinux-97621d22df60d7348826d2e4b0c349673faeb4b8.tar.xz
clk: stm32mp1: fix bit width of hse_rtc divider
Fix the bit width of the hse rtc divider because it's off by one. Fixes: 2c87c9d33117 ("clk: stm32mp1: add RTC clock") Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-stm32mp1.c')
-rw-r--r--drivers/clk/clk-stm32mp1.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index ca987632564e..a0ae8dc16909 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1962,7 +1962,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
/* RTC clock */
- DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0),
+ DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
CLK_SET_RATE_PARENT,