diff options
| author | Tom St Denis <tom.stdenis@amd.com> | 2020-06-11 14:54:13 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 08:59:19 +0300 |
| commit | 8d7fb7a10a825bd2e2c0fde7979cd8774c332bea (patch) | |
| tree | 18230fd18156acb229eee5b2efe95b5633b83163 /drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | |
| parent | 651a146526a04993c5bebf0e19cd9256f5e6511d (diff) | |
| download | linux-8d7fb7a10a825bd2e2c0fde7979cd8774c332bea.tar.xz | |
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.
Requested for UMR debugging.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h index 791dc2b3d74a..aab3d22c3b0f 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h @@ -21,7 +21,8 @@ #ifndef _gc_10_1_0_OFFSET_HEADER #define _gc_10_1_0_OFFSET_HEADER - +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 // addressBlock: gc_sdma0_sdma0dec // base address: 0x4980 |