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authorChris Wilson <chris@chris-wilson.co.uk>2019-01-28 21:18:08 +0300
committerChris Wilson <chris@chris-wilson.co.uk>2019-01-28 22:07:01 +0300
commitb18fe4be59f215b1ce75f406d04810454f206faf (patch)
tree5c456c8725328a35648dbf677ae7f99033be1a1a /drivers/gpu/drm/i915/i915_timeline.c
parent3adac4689f58cb3fb666d92dff0ee73cc97d24d7 (diff)
downloadlinux-b18fe4be59f215b1ce75f406d04810454f206faf.tar.xz
drm/i915: Enlarge vma->pin_count
Previously we only accommodated having a vma pinned by a small number of users, with the maximum being pinned for use by the display engine. As such, we used a small bitfield only large enough to allow the vma to be pinned twice (for back/front buffers) in each scanout plane. Keeping the maximum permissible pin_count small allows us to quickly catch a potential leak. However, as we want to split a 4096B page into 64 different cachelines and pin each cacheline for use by a different timeline, we will exceed the current maximum permissible vma->pin_count and so time has come to enlarge it. Whilst we are here, try to pull together the similar bits: Address/layout specification: - bias, mappable, zone_4g: address limit specifiers - fixed: address override, limits still apply though - high: not strictly an address limit, but an address direction to search Search controls: - nonblock, nonfault, noevict v2: Rewrite the guideline comment on bit consumption. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: John Harrison <john.C.Harrison@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190128181812.22804-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_timeline.c')
0 files changed, 0 insertions, 0 deletions