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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2020-02-18 19:21:48 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-02-19 17:09:18 +0300 |
| commit | 0e744b519fa18abb92bcd73a611777a6c6f591ba (patch) | |
| tree | 4ba04cf036d504537061c7e801d1415c4621c250 /drivers/gpu/drm/i915/intel_device_info.c | |
| parent | f20a60fb7aef3f5aecee4a9c30e36ee3e518fa16 (diff) | |
| download | linux-0e744b519fa18abb92bcd73a611777a6c6f591ba.tar.xz | |
drm/i915/gt: Refactor l3cc/mocs availability
On dgfx, we only use l3cc and not mocs, but we share the table
containing both register definitions with Tigerlake. This confuses our
selftest that verifies that both sets of registers do contain the values
in our tables after various events (idling, reset, activity etc).
When constructing the table of register definitions, also include the
flags for which registers are valid so that information is computed
centrally and available to all callers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200218162150.1300405-10-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_device_info.c')
0 files changed, 0 insertions, 0 deletions