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author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-10-15 17:27:54 +0300 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2018-10-22 09:44:30 +0300 |
commit | e72cce53101767230b7800c5b6e6341aaa451632 (patch) | |
tree | eff9fc476b828a3a3abde0b04463013d20513dce /drivers/gpu/drm/i915/intel_dsi.h | |
parent | b687c1984c4fbb40ba9058c5db9a604ffc466f5e (diff) | |
download | linux-e72cce53101767230b7800c5b6e6341aaa451632.tar.xz |
drm/i915/icl: Program DSI clock and data lane timing params
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
v2: Use newly defined bitfields for data and clock lane
v3 by Jani:
- Rebase on dphy abstraction
- Reduce local variables
- Remove unrelated comment changes (Ville)
- Use the same style for range checks as VLV (Ville)
- Assign, don't OR dphy_reg contents
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/70d491e2357f328a63b67ea3c43cb57a1d469c15.1539613303.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dsi.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index d7c0c599b52d..12b758ebefce 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -85,6 +85,9 @@ struct intel_dsi { u32 port_bits; u32 bw_timer; u32 dphy_reg; + + /* data lanes dphy timing */ + u32 dphy_data_lane_reg; u32 video_frmt_cfg_bits; u16 lp_byte_clk; |