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authorAlex Deucher <alexdeucher@gmail.com>2009-12-02 08:59:37 +0300
committerDave Airlie <airlied@redhat.com>2009-12-04 03:24:11 +0300
commit4c4f5413c3208da7621cd29baac1fbdca89181b2 (patch)
tree985ba67a419c220441385e56869b7a0301ed61d5 /drivers/gpu/drm/radeon/radeon_legacy_crtc.c
parentd684076627a4561ea698bf7652a1a1baabdcdbdc (diff)
downloadlinux-4c4f5413c3208da7621cd29baac1fbdca89181b2.tar.xz
drm/radeon/kms: don't use bios dividers for lvds on r4xx
R4xx cards don't have lvds pll dividers since they use atom. should fix rh bug 541562 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_legacy_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index c1e1706d06b4..6f3ff8b84faf 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -796,18 +796,20 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
- struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
- struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
- if (lvds) {
- if (lvds->use_bios_dividers) {
- pll_ref_div = lvds->panel_ref_divider;
- pll_fb_post_div = (lvds->panel_fb_divider |
- (lvds->panel_post_divider << 16));
- htotal_cntl = 0;
- use_bios_divs = true;
+ if (!rdev->is_atom_bios) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
+ if (lvds) {
+ if (lvds->use_bios_dividers) {
+ pll_ref_div = lvds->panel_ref_divider;
+ pll_fb_post_div = (lvds->panel_fb_divider |
+ (lvds->panel_post_divider << 16));
+ htotal_cntl = 0;
+ use_bios_divs = true;
+ }
}
+ pll_flags |= RADEON_PLL_USE_REF_DIV;
}
- pll_flags |= RADEON_PLL_USE_REF_DIV;
}
}
}