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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2015-01-06 13:01:26 +0300
committerMark Brown <broonie@kernel.org>2015-01-06 14:04:33 +0300
commit6d40530e4789b3e2f14d61ca57ab02bd5395d5c9 (patch)
tree6f07814434fe8bf29b5d49478176f11b31208726 /drivers/spi/spi-sh-msiof.c
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
downloadlinux-6d40530e4789b3e2f14d61ca57ab02bd5395d5c9.tar.xz
spi: sh-msiof: fix MDR1_FLD_MASK value
Since the FLD bit field is bit[3:2], the MDR1_FLD_MASK value should be 0x0000000c. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-sh-msiof.c')
-rw-r--r--drivers/spi/spi-sh-msiof.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 239be7cbe5a8..87253eaadd4c 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -82,7 +82,7 @@ struct sh_msiof_spi_priv {
#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
-#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */
+#define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
#define MDR1_FLD_SHIFT 2
#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
/* TMDR1 */