diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/amd_powerplay.c')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 528 |
1 files changed, 246 insertions, 282 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index f73e80c4bf33..c7e34128cbde 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -29,72 +29,98 @@ #include "amd_powerplay.h" #include "pp_instance.h" #include "power_state.h" -#include "eventmanager.h" +#define PP_DPM_DISABLED 0xCCCC + +static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, + void *input, void *output); static inline int pp_check(struct pp_instance *handle) { - if (handle == NULL || handle->pp_valid != PP_VALID) + if (handle == NULL) return -EINVAL; - if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL) + if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL) return -EINVAL; if (handle->pm_en == 0) return PP_DPM_DISABLED; - if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL - || handle->eventmgr == NULL) + if (handle->hwmgr->hwmgr_func == NULL) return PP_DPM_DISABLED; return 0; } +static int amd_powerplay_create(struct amd_pp_init *pp_init, + void **handle) +{ + struct pp_instance *instance; + + if (pp_init == NULL || handle == NULL) + return -EINVAL; + + instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL); + if (instance == NULL) + return -ENOMEM; + + instance->chip_family = pp_init->chip_family; + instance->chip_id = pp_init->chip_id; + instance->pm_en = pp_init->pm_en; + instance->feature_mask = pp_init->feature_mask; + instance->device = pp_init->device; + mutex_init(&instance->pp_lock); + *handle = instance; + return 0; +} + +static int amd_powerplay_destroy(void *handle) +{ + struct pp_instance *instance = (struct pp_instance *)handle; + + kfree(instance->hwmgr->hardcode_pp_table); + instance->hwmgr->hardcode_pp_table = NULL; + + kfree(instance->hwmgr); + instance->hwmgr = NULL; + + kfree(instance); + instance = NULL; + return 0; +} + static int pp_early_init(void *handle) { int ret; - struct pp_instance *pp_handle = (struct pp_instance *)handle; + struct pp_instance *pp_handle = NULL; - ret = smum_early_init(pp_handle); - if (ret) - return ret; + pp_handle = cgs_register_pp_handle(handle, amd_powerplay_create); - if ((pp_handle->pm_en == 0) - || cgs_is_virtualization_enabled(pp_handle->device)) - return PP_DPM_DISABLED; + if (!pp_handle) + return -EINVAL; ret = hwmgr_early_init(pp_handle); - if (ret) { - pp_handle->pm_en = 0; - return PP_DPM_DISABLED; - } - - ret = eventmgr_early_init(pp_handle); - if (ret) { - kfree(pp_handle->hwmgr); - pp_handle->hwmgr = NULL; - pp_handle->pm_en = 0; - return PP_DPM_DISABLED; - } + if (ret) + return -EINVAL; return 0; } static int pp_sw_init(void *handle) { - struct pp_smumgr *smumgr; + struct pp_hwmgr *hwmgr; int ret = 0; struct pp_instance *pp_handle = (struct pp_instance *)handle; ret = pp_check(pp_handle); - if (ret == 0 || ret == PP_DPM_DISABLED) { - smumgr = pp_handle->smu_mgr; + if (ret >= 0) { + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->smu_init == NULL) + if (hwmgr->smumgr_funcs->smu_init == NULL) return -EINVAL; - ret = smumgr->smumgr_funcs->smu_init(smumgr); + ret = hwmgr->smumgr_funcs->smu_init(hwmgr); pr_info("amdgpu: powerplay sw initialized\n"); } @@ -103,84 +129,86 @@ static int pp_sw_init(void *handle) static int pp_sw_fini(void *handle) { - struct pp_smumgr *smumgr; + struct pp_hwmgr *hwmgr; int ret = 0; struct pp_instance *pp_handle = (struct pp_instance *)handle; ret = pp_check(pp_handle); - if (ret == 0 || ret == PP_DPM_DISABLED) { - smumgr = pp_handle->smu_mgr; + if (ret >= 0) { + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->smu_fini == NULL) + if (hwmgr->smumgr_funcs->smu_fini == NULL) return -EINVAL; - ret = smumgr->smumgr_funcs->smu_fini(smumgr); + ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); } return ret; } static int pp_hw_init(void *handle) { - struct pp_smumgr *smumgr; - struct pp_eventmgr *eventmgr; int ret = 0; struct pp_instance *pp_handle = (struct pp_instance *)handle; + struct pp_hwmgr *hwmgr; ret = pp_check(pp_handle); - if (ret == 0 || ret == PP_DPM_DISABLED) { - smumgr = pp_handle->smu_mgr; + if (ret >= 0) { + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->start_smu == NULL) + if (hwmgr->smumgr_funcs->start_smu == NULL) return -EINVAL; - if(smumgr->smumgr_funcs->start_smu(smumgr)) { + if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) { pr_err("smc start failed\n"); - smumgr->smumgr_funcs->smu_fini(smumgr); + hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); return -EINVAL;; } if (ret == PP_DPM_DISABLED) - return PP_DPM_DISABLED; + goto exit; + ret = hwmgr_hw_init(pp_handle); + if (ret) + goto exit; } - - ret = hwmgr_hw_init(pp_handle); - if (ret) - goto err; - - eventmgr = pp_handle->eventmgr; - if (eventmgr->pp_eventmgr_init == NULL || - eventmgr->pp_eventmgr_init(eventmgr)) - goto err; - - return 0; -err: + return ret; +exit: pp_handle->pm_en = 0; - kfree(pp_handle->eventmgr); - kfree(pp_handle->hwmgr); - pp_handle->hwmgr = NULL; - pp_handle->eventmgr = NULL; - return PP_DPM_DISABLED; + cgs_notify_dpm_enabled(hwmgr->device, false); + return 0; + } static int pp_hw_fini(void *handle) { - struct pp_eventmgr *eventmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; ret = pp_check(pp_handle); + if (ret == 0) + hwmgr_hw_fini(pp_handle); + + return 0; +} - if (ret == 0) { - eventmgr = pp_handle->eventmgr; +static int pp_late_init(void *handle) +{ + struct pp_instance *pp_handle = (struct pp_instance *)handle; + int ret = 0; - if (eventmgr->pp_eventmgr_fini != NULL) - eventmgr->pp_eventmgr_fini(eventmgr); + ret = pp_check(pp_handle); + if (ret == 0) + pp_dpm_dispatch_tasks(pp_handle, + AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); - hwmgr_hw_fini(pp_handle); - } return 0; } +static void pp_late_fini(void *handle) +{ + amd_powerplay_destroy(handle); +} + + static bool pp_is_idle(void *handle) { return false; @@ -196,28 +224,6 @@ static int pp_sw_reset(void *handle) return 0; } - -int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id) -{ - struct pp_hwmgr *hwmgr; - struct pp_instance *pp_handle = (struct pp_instance *)handle; - int ret = 0; - - ret = pp_check(pp_handle); - - if (ret != 0) - return ret; - - hwmgr = pp_handle->hwmgr; - - if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { - pr_info("%s was not implemented.\n", __func__); - return 0; - } - - return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); -} - static int pp_set_powergating_state(void *handle, enum amd_powergating_state state) { @@ -227,7 +233,7 @@ static int pp_set_powergating_state(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -244,67 +250,52 @@ static int pp_set_powergating_state(void *handle, static int pp_suspend(void *handle) { - struct pp_eventmgr *eventmgr; - struct pem_event_data event_data = { {0} }; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; ret = pp_check(pp_handle); - - if (ret == PP_DPM_DISABLED) - return 0; - else if (ret != 0) - return ret; - - eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); - + if (ret == 0) + hwmgr_hw_suspend(pp_handle); return 0; } static int pp_resume(void *handle) { - struct pp_eventmgr *eventmgr; - struct pem_event_data event_data = { {0} }; - struct pp_smumgr *smumgr; - int ret, ret1; + struct pp_hwmgr *hwmgr; + int ret; struct pp_instance *pp_handle = (struct pp_instance *)handle; - ret1 = pp_check(pp_handle); + ret = pp_check(pp_handle); - if (ret1 != 0 && ret1 != PP_DPM_DISABLED) - return ret1; + if (ret < 0) + return ret; - smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->start_smu == NULL) + if (hwmgr->smumgr_funcs->start_smu == NULL) return -EINVAL; - ret = smumgr->smumgr_funcs->start_smu(smumgr); - if (ret) { + if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) { pr_err("smc start failed\n"); - smumgr->smumgr_funcs->smu_fini(smumgr); - return ret; + hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); + return -EINVAL; } - if (ret1 == PP_DPM_DISABLED) + if (ret == PP_DPM_DISABLED) return 0; - eventmgr = pp_handle->eventmgr; - - pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); - - return 0; + return hwmgr_hw_resume(pp_handle); } const struct amd_ip_funcs pp_ip_funcs = { .name = "powerplay", .early_init = pp_early_init, - .late_init = NULL, + .late_init = pp_late_init, .sw_init = pp_sw_init, .sw_fini = pp_sw_fini, .hw_init = pp_hw_init, .hw_fini = pp_hw_fini, + .late_fini = pp_late_fini, .suspend = pp_suspend, .resume = pp_resume, .is_idle = pp_is_idle, @@ -324,6 +315,63 @@ static int pp_dpm_fw_loading_complete(void *handle) return 0; } +static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) +{ + struct pp_hwmgr *hwmgr; + struct pp_instance *pp_handle = (struct pp_instance *)handle; + int ret = 0; + + ret = pp_check(pp_handle); + + if (ret) + return ret; + + hwmgr = pp_handle->hwmgr; + + if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { + pr_info("%s was not implemented.\n", __func__); + return 0; + } + + return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); +} + +static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, + enum amd_dpm_forced_level *level) +{ + uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | + AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; + + if (!(hwmgr->dpm_level & profile_mode_mask)) { + /* enter umd pstate, save current level, disable gfx cg*/ + if (*level & profile_mode_mask) { + hwmgr->saved_dpm_level = hwmgr->dpm_level; + hwmgr->en_umd_pstate = true; + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_CG_STATE_UNGATE); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_PG_STATE_UNGATE); + } + } else { + /* exit umd pstate, restore level, enable gfx cg*/ + if (!(*level & profile_mode_mask)) { + if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) + *level = hwmgr->saved_dpm_level; + hwmgr->en_umd_pstate = false; + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_CG_STATE_GATE); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_PG_STATE_GATE); + } + } +} + static int pp_dpm_force_performance_level(void *handle, enum amd_dpm_forced_level level) { @@ -333,18 +381,27 @@ static int pp_dpm_force_performance_level(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; + if (level == hwmgr->dpm_level) + return 0; + if (hwmgr->hwmgr_func->force_dpm_level == NULL) { pr_info("%s was not implemented.\n", __func__); return 0; } mutex_lock(&pp_handle->pp_lock); - hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); + pp_dpm_en_umd_pstate(hwmgr, &level); + hwmgr->request_dpm_level = level; + hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); + ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); + if (!ret) + hwmgr->dpm_level = hwmgr->request_dpm_level; + mutex_unlock(&pp_handle->pp_lock); return 0; } @@ -359,7 +416,7 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -369,15 +426,16 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( return level; } -static int pp_dpm_get_sclk(void *handle, bool low) +static uint32_t pp_dpm_get_sclk(void *handle, bool low) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; + uint32_t clk = 0; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -387,20 +445,21 @@ static int pp_dpm_get_sclk(void *handle, bool low) return 0; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->get_sclk(hwmgr, low); + clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low); mutex_unlock(&pp_handle->pp_lock); - return ret; + return clk; } -static int pp_dpm_get_mclk(void *handle, bool low) +static uint32_t pp_dpm_get_mclk(void *handle, bool low) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; + uint32_t clk = 0; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -410,12 +469,12 @@ static int pp_dpm_get_mclk(void *handle, bool low) return 0; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->get_mclk(hwmgr, low); + clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low); mutex_unlock(&pp_handle->pp_lock); - return ret; + return clk; } -static int pp_dpm_powergate_vce(void *handle, bool gate) +static void pp_dpm_powergate_vce(void *handle, bool gate) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -423,22 +482,21 @@ static int pp_dpm_powergate_vce(void *handle, bool gate) ret = pp_check(pp_handle); - if (ret != 0) - return ret; + if (ret) + return; hwmgr = pp_handle->hwmgr; if (hwmgr->hwmgr_func->powergate_vce == NULL) { pr_info("%s was not implemented.\n", __func__); - return 0; + return; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); + hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); mutex_unlock(&pp_handle->pp_lock); - return ret; } -static int pp_dpm_powergate_uvd(void *handle, bool gate) +static void pp_dpm_powergate_uvd(void *handle, bool gate) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -446,75 +504,35 @@ static int pp_dpm_powergate_uvd(void *handle, bool gate) ret = pp_check(pp_handle); - if (ret != 0) - return ret; + if (ret) + return; hwmgr = pp_handle->hwmgr; if (hwmgr->hwmgr_func->powergate_uvd == NULL) { pr_info("%s was not implemented.\n", __func__); - return 0; + return; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); + hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); mutex_unlock(&pp_handle->pp_lock); - return ret; -} - -static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) -{ - switch (state) { - case POWER_STATE_TYPE_BATTERY: - return PP_StateUILabel_Battery; - case POWER_STATE_TYPE_BALANCED: - return PP_StateUILabel_Balanced; - case POWER_STATE_TYPE_PERFORMANCE: - return PP_StateUILabel_Performance; - default: - return PP_StateUILabel_None; - } } -static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, +static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, void *input, void *output) { int ret = 0; - struct pem_event_data data = { {0} }; struct pp_instance *pp_handle = (struct pp_instance *)handle; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; - mutex_lock(&pp_handle->pp_lock); - switch (event_id) { - case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - case AMD_PP_EVENT_ENABLE_USER_STATE: - { - enum amd_pm_state_type ps; - - if (input == NULL) { - ret = -EINVAL; - break; - } - ps = *(unsigned long *)input; - data.requested_ui_label = power_state_convert(ps); - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - } - case AMD_PP_EVENT_COMPLETE_INIT: - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - case AMD_PP_EVENT_READJUST_POWER_STATE: - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - default: - break; - } + mutex_lock(&pp_handle->pp_lock); + ret = hwmgr_handle_task(pp_handle, task_id, input, output); mutex_unlock(&pp_handle->pp_lock); + return ret; } @@ -528,7 +546,7 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -562,7 +580,7 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) return pm_type; } -static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) +static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -570,30 +588,30 @@ static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) ret = pp_check(pp_handle); - if (ret != 0) - return ret; + if (ret) + return; hwmgr = pp_handle->hwmgr; if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { pr_info("%s was not implemented.\n", __func__); - return 0; + return; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); + hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); mutex_unlock(&pp_handle->pp_lock); - return ret; } -static int pp_dpm_get_fan_control_mode(void *handle) +static uint32_t pp_dpm_get_fan_control_mode(void *handle) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; + uint32_t mode = 0; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -603,9 +621,9 @@ static int pp_dpm_get_fan_control_mode(void *handle) return 0; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); + mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); mutex_unlock(&pp_handle->pp_lock); - return ret; + return mode; } static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) @@ -616,7 +634,7 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -639,7 +657,7 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -663,7 +681,7 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -685,7 +703,7 @@ static int pp_dpm_get_temperature(void *handle) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -710,7 +728,7 @@ static int pp_dpm_get_pp_num_states(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -755,7 +773,7 @@ static int pp_dpm_get_pp_table(void *handle, char **table) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -778,7 +796,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -820,7 +838,7 @@ static int pp_dpm_force_clock_level(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -844,7 +862,7 @@ static int pp_dpm_print_clock_levels(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -867,7 +885,7 @@ static int pp_dpm_get_sclk_od(void *handle) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -890,7 +908,7 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -914,7 +932,7 @@ static int pp_dpm_get_mclk_od(void *handle) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -937,7 +955,7 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -961,7 +979,7 @@ static int pp_dpm_read_sensor(void *handle, int idx, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -987,7 +1005,7 @@ pp_dpm_get_vce_clock_state(void *handle, unsigned idx) ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return NULL; hwmgr = pp_handle->hwmgr; @@ -1128,7 +1146,7 @@ static int pp_dpm_switch_power_profile(void *handle, return 0; } -const struct amd_powerplay_funcs pp_dpm_funcs = { +const struct amd_pm_funcs pp_dpm_funcs = { .get_temperature = pp_dpm_get_temperature, .load_firmware = pp_dpm_load_fw, .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, @@ -1160,81 +1178,27 @@ const struct amd_powerplay_funcs pp_dpm_funcs = { .get_power_profile_state = pp_dpm_get_power_profile_state, .set_power_profile_state = pp_dpm_set_power_profile_state, .switch_power_profile = pp_dpm_switch_power_profile, + .set_clockgating_by_smu = pp_set_clockgating_by_smu, }; -int amd_powerplay_create(struct amd_pp_init *pp_init, - void **handle) -{ - struct pp_instance *instance; - - if (pp_init == NULL || handle == NULL) - return -EINVAL; - - instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL); - if (instance == NULL) - return -ENOMEM; - - instance->pp_valid = PP_VALID; - instance->chip_family = pp_init->chip_family; - instance->chip_id = pp_init->chip_id; - instance->pm_en = pp_init->pm_en; - instance->feature_mask = pp_init->feature_mask; - instance->device = pp_init->device; - mutex_init(&instance->pp_lock); - *handle = instance; - return 0; -} - -int amd_powerplay_destroy(void *handle) -{ - struct pp_instance *instance = (struct pp_instance *)handle; - - if (instance->pm_en) { - kfree(instance->eventmgr); - kfree(instance->hwmgr); - instance->hwmgr = NULL; - instance->eventmgr = NULL; - } - - kfree(instance->smu_mgr); - instance->smu_mgr = NULL; - kfree(instance); - instance = NULL; - return 0; -} - int amd_powerplay_reset(void *handle) { struct pp_instance *instance = (struct pp_instance *)handle; - struct pp_eventmgr *eventmgr; - struct pem_event_data event_data = { {0} }; int ret; - if (cgs_is_virtualization_enabled(instance->smu_mgr->device)) - return PP_DPM_DISABLED; - ret = pp_check(instance); - if (ret != 0) + if (ret) return ret; - ret = pp_hw_fini(handle); + ret = pp_hw_fini(instance); if (ret) return ret; ret = hwmgr_hw_init(instance); if (ret) - return PP_DPM_DISABLED; - - eventmgr = instance->eventmgr; - - if (eventmgr->pp_eventmgr_init == NULL) - return PP_DPM_DISABLED; - - ret = eventmgr->pp_eventmgr_init(eventmgr); - if (ret) return ret; - return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data); + return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); } /* export this function to DAL */ @@ -1248,7 +1212,7 @@ int amd_powerplay_display_configuration_change(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -1267,7 +1231,7 @@ int amd_powerplay_get_display_power_level(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -1292,7 +1256,7 @@ int amd_powerplay_get_current_clocks(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -1309,7 +1273,7 @@ int amd_powerplay_get_current_clocks(void *handle, ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity); - if (ret != 0) { + if (ret) { pr_info("Error in phm_get_clock_info \n"); mutex_unlock(&pp_handle->pp_lock); return -EINVAL; @@ -1343,7 +1307,7 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; @@ -1366,7 +1330,7 @@ int amd_powerplay_get_clock_by_type_with_latency(void *handle, int ret = 0; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; if (!clocks) @@ -1388,7 +1352,7 @@ int amd_powerplay_get_clock_by_type_with_voltage(void *handle, int ret = 0; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; if (!clocks) @@ -1412,7 +1376,7 @@ int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, int ret = 0; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; if (!wm_with_clock_ranges) @@ -1436,7 +1400,7 @@ int amd_powerplay_display_clock_voltage_request(void *handle, int ret = 0; ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; if (!clock) @@ -1460,7 +1424,7 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle, ret = pp_check(pp_handle); - if (ret != 0) + if (ret) return ret; hwmgr = pp_handle->hwmgr; |