index
:
BMC/Intel-BMC/linux.git
dev
dev-4.10
dev-4.13
dev-4.17
dev-4.18
dev-4.19
dev-4.3
dev-4.4
dev-4.6
dev-4.7
dev-5.0
dev-5.1
dev-5.10-intel
dev-5.10.46-intel
dev-5.10.49-intel
dev-5.14-intel
dev-5.15-intel
dev-5.2
dev-5.3
dev-5.4
dev-5.7
dev-5.8
dev-5.8-intel
master
Intel OpenBMC Linux kernel source tree (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
riscv
/
configs
/
defconfig
Age
Commit message (
Expand
)
Author
Files
Lines
2019-08-14
riscv: defconfig: Update the defconfig
Alistair Francis
1
-0
/
+2
2019-07-31
riscv: defconfig: align RV64 defconfig to the output of "make savedefconfig"
Paul Walmsley
1
-5
/
+5
2019-07-01
riscv: defconfig: enable SOC_SIFIVE
Loys Ollivier
1
-5
/
+1
2019-07-01
RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS
Anup Patel
1
-0
/
+2
2019-06-26
RISC-V: defconfig: enable MMC & SPI for RISC-V
Atish Patra
1
-0
/
+5
2019-06-11
RISC-V: defconfig: enable clocks, serial console
Kevin Hilman
1
-0
/
+4
2019-01-24
RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=y
Palmer Dabbelt
1
-0
/
+1
2019-01-24
RISC-V: defconfig: Enable Generic PCIE by default
Alistair Francis
1
-1
/
+2
2019-01-23
RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX}
Palmer Dabbelt
1
-2
/
+2
2018-12-17
RISC-V: defconfig: Enable RISC-V SBI earlycon support
Anup Patel
1
-0
/
+1
2018-11-13
RISC-V: defconfig: Enable printk timestamps
Anup Patel
1
-0
/
+1
2018-11-02
RISC-V: refresh defconfig
Anup Patel
1
-8
/
+8
2018-08-13
irqchip: add a SiFive PLIC driver
Christoph Hellwig
1
-0
/
+1
2018-06-11
RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
Palmer Dabbelt
1
-0
/
+1
2018-04-03
RISC-V: Enable module support in defconfig
Zong Li
1
-0
/
+2
2018-01-08
RISC-V: Add a basic defconfig
Karsten Merker
1
-0
/
+75
2017-09-27
RISC-V: Build Infrastructure
Palmer Dabbelt
1
-0
/
+0