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path: root/drivers/clk/imx/clk.h
AgeCommit message (Expand)AuthorFilesLines
2020-08-22clk: imx: Explicitly include bits.hAnson Huang1-0/+1
2020-08-22clk: imx: Support building i.MX common clock driver as moduleAnson Huang1-0/+6
2020-05-21clk: imx: add imx8m_clk_hw_composite_busPeng Fan1-0/+7
2020-04-29clk: imx: Add helpers for passing the device as argumentAbel Vesa1-0/+29
2020-04-29clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa1-3/+10
2020-04-29clk: imx: gate2: Allow single bit gating clockAbel Vesa1-0/+13
2020-02-14clk: imx: composite-8m: add imx8m_clk_hw_composite_corePeng Fan1-2/+11
2020-01-12clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based APIAnson Huang1-2/+5
2019-12-23clk: imx: gate3: Switch to clk_hw based APIPeng Fan1-2/+5
2019-12-23clk: imx: add hw API imx_clk_hw_mux2_flagsPeng Fan1-0/+10
2019-12-23clk: imx: add imx_unregister_hw_clocksPeng Fan1-0/+1
2019-12-23clk: imx: clk-composite-8m: Switch to clk_hw based APIPeng Fan1-7/+22
2019-12-23clk: imx: clk-pll14xx: Switch to clk_hw based APIPeng Fan1-0/+7
2019-12-11clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw basedAbel Vesa1-1/+1
2019-12-11clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw basedAbel Vesa1-1/+1
2019-12-11clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw basedAbel Vesa1-1/+1
2019-12-11clk: imx: Rename sccg and frac pll register to suggest clk_hwAbel Vesa1-2/+10
2019-12-11clk: imx: imx7ulp composite: Rename to show is clk_hw basedAbel Vesa1-1/+1
2019-12-11clk: imx: pllv2: Switch to clk_hw based APIAbel Vesa1-1/+4
2019-12-11clk: imx: pllv1: Switch to clk_hw based APIAbel Vesa1-1/+4
2019-12-11clk: imx: Replace all the clk based helpers with macrosAbel Vesa1-27/+12
2019-12-11clk: imx: Rename the SCCG to SSCGAbel Vesa1-2/+2
2019-12-11clk: imx: Add correct failure handling for clk based helpersAbel Vesa1-15/+22
2019-12-09clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHELeonard Crestez1-0/+1
2019-10-06clk: imx8mm: Move 1443X/1416X PLL clock structure to common placeAnson Huang1-0/+3
2019-08-03clk: imx: Remove unused function statementAnson Huang1-1/+0
2019-08-03clk: imx: Remove unused clk based APIAbel Vesa1-24/+0
2019-08-03clk: imx: Add API for clk unregister when driver probe failAnson Huang1-0/+1
2019-08-03clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usageAnson Huang1-0/+17
2019-06-07clk: imx: Switch wrappers to clk_hw based APIAbel Vesa1-26/+65
2019-06-07clk: imx: clk-fixup-mux: Switch to clk_hw based APIAbel Vesa1-0/+3
2019-06-07clk: imx: clk-fixup-div: Switch to clk_hw based APIAbel Vesa1-2/+5
2019-06-07clk: imx: clk-gate-exclusive: Switch to clk_hw based APIAbel Vesa1-1/+4
2019-06-07clk: imx: clk-pfd: Switch to clk_hw based APIAbel Vesa1-1/+4
2019-06-07clk: imx: clk-pllv3: Switch to clk_hw based APIAbel Vesa1-1/+4
2019-06-07clk: imx: clk-gate2: Switch to clk_hw based APIAbel Vesa1-1/+6
2019-06-07clk: imx: clk-cpu: Switch to clk_hw based APIAbel Vesa1-1/+4
2019-06-07clk: imx: clk-busy: Switch to clk_hw based APIAbel Vesa1-2/+9
2019-06-07clk: imx: Add imx_obtain_fixed_clock clk_hw based variantAbel Vesa1-0/+3
2019-05-23clk: imx: Add common API for masking MMDC handshakeAnson Huang1-0/+1
2019-04-30clk: imx: correct i.MX7D AV PLL num/denom offsetAnson Huang1-0/+1
2019-03-26clk: imx: Remove unused imx_get_clk_hw_fixedAbel Vesa1-5/+0
2019-02-26clk: imx: Refactor entire sccg pll clkAbel Vesa1-3/+6
2019-02-21clk: imx: Add PLLs driver for imx8mm socBai Ping1-0/+24
2019-02-21clk: imx: Make parents const pointer in mux wrappersAbel Vesa1-1/+2
2019-02-21clk: imx: Make parent_names const pointer in composite-8mAbel Vesa1-1/+1
2018-12-15Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp...Stephen Boyd1-7/+153
2018-12-03clk: imx: implement new clk_hw based APIsA.s. Dong1-0/+62
2018-12-03clk: imx: make mux parent strings constA.s. Dong1-7/+11
2018-12-03clk: imx: add imx7ulp composite clk supportA.s. Dong1-0/+6