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path: root/drivers/clk/ingenic
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2020-10-14clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil1-0/+2
2020-10-14clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil1-7/+7
2020-10-14clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil1-2/+7
2020-10-14clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil1-26/+29
2020-10-14clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil1-39/+15
2020-07-28clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)1-1/+83
2020-07-28clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)1-45/+45
2020-07-28clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)1-30/+35
2020-07-28clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)3-0/+38
2020-05-29clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd1-1/+1
2020-05-29clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)1-6/+111
2020-05-29clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)3-0/+459
2020-05-29clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)7-4/+41
2020-05-29clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)1-11/+1
2020-03-21clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil1-1/+1
2020-03-21clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil1-1/+3
2020-03-21clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)1-5/+50
2020-03-21clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)1-0/+8
2019-11-27Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd3-1/+286
2019-11-22clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd1-1/+1
2019-11-14clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie3-0/+285
2019-11-08drivers/clk: convert VL struct to struct_sizeStephen Kitt1-2/+1
2019-09-22Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds4-1/+490
2019-08-12clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil4-4/+4
2019-08-09clk: jz4740: Add TCU clockPaul Cercueil1-0/+6
2019-08-09clk: ingenic: Add driver for the TCU clocksPaul Cercueil3-1/+484
2019-08-08clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil1-1/+8
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds9-128/+192
2019-06-26clk: ingenic: Remove unused functionsPaul Cercueil1-73/+0
2019-06-26clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil7-32/+69
2019-06-26clk: ingenic: Add missing header in cgu.hPaul Cercueil1-0/+1
2019-06-07clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil1-1/+8
2019-06-07clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
2019-06-07clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil1-6/+28
2019-06-07clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil1-5/+24
2019-06-07clk: ingenic: Add support for divider tablesPaul Cercueil2-6/+38
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner4-40/+4
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2-0/+2
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd4-0/+4
2019-04-11clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil1-0/+6
2019-02-26clk: ingenic: Remove set but not used variable 'enable'YueHaibing1-2/+1
2019-02-22clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil1-1/+1
2019-02-22clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil1-5/+5
2019-02-06clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil1-1/+1
2018-10-17clk: Add Ingenic jz4725b CGU driverPaul Cercueil3-0/+236
2018-10-17clk: ingenic: Add proper Kconfig entriesPaul Cercueil2-4/+41
2018-07-06clk: ingenic: Add missing flag for UDC clockPaul Cercueil1-1/+1
2018-07-06clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil1-1/+1
2018-06-16docs: Fix some broken referencesMauro Carvalho Chehab1-1/+1
2018-06-02clk: ingenic: jz4770: Add 150us delay after enabling VPU clockPaul Cercueil1-1/+1