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path: root/drivers/clk/meson/axg.h
AgeCommit message (Expand)AuthorFilesLines
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet1-1/+7
2018-07-09clk: meson: add gen_clkJerome Brunet1-1/+3
2018-07-09clk: meson-axg: add clocks required by pcie driverYixun Lan1-1/+5
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet1-1/+6
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet1-1/+2
2018-03-13clk: meson: axg: add hifi pll clockJerome Brunet1-1/+1
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet1-1/+5
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai1-0/+126