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path: root/drivers/clk/pistachio
AgeCommit message (Expand)AuthorFilesLines
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422Thomas Gleixner4-16/+4
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2018-11-06clk: pistachio: constify clk_ops structuresJulia Lawall1-4/+4
2015-08-26clk: pistachio: correct critical clock listDamien.Horsley1-5/+14
2015-08-26clk: pistachio: Fix PLL rate calculation in integer modeZdenko Pulitika1-2/+46
2015-08-26clk: pistachio: Fix override of clk-pll settings from boot loaderZdenko Pulitika1-3/+2
2015-08-26clk: pistachio: Fix 32bit integer overflowsZdenko Pulitika2-21/+19
2015-08-25clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd1-2/+2
2015-07-20clk: pistachio: Include clk.hStephen Boyd1-0/+1
2015-06-04clk: pistachio: Add sanity checks on PLL configurationKevin Cernekee1-4/+79
2015-06-04clk: pistachio: Lock the PLL when enabled upon rate changeEzequiel Garcia1-18/+10
2015-06-04clk: pistachio: Add a pll_lock() helper for clarityEzequiel Garcia1-4/+8
2015-03-31CLK: Pistachio: Register external clock gatesAndrew Bresticker1-0/+21
2015-03-31CLK: Pistachio: Register system interface gate clocksAndrew Bresticker1-0/+42
2015-03-31CLK: Pistachio: Register peripheral clocksAndrew Bresticker1-0/+67
2015-03-31CLK: Pistachio: Register core clocksAndrew Bresticker2-0/+200
2015-03-31CLK: Pistachio: Add PLL driverAndrew Bresticker3-0/+452
2015-03-31CLK: Add basic infrastructure for Pistachio clocksAndrew Bresticker3-0/+265