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path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd8-0/+8
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd3-6/+6
2019-05-01clk: renesas: Use the correct style for SPDX License IdentifierNishad Kamdar3-6/+6
2019-04-11clk: renesas: rcar-gen3: Remove unused variableStephen Boyd1-1/+0
2019-04-04clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return valueTakeshi Kihara1-16/+14
2019-04-02clk: renesas: r8a77980: Fix RPC-IF module clock's parentSergei Shtylyov1-1/+1
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara4-34/+35
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara7-11/+11
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara4-8/+8
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi6-7/+7
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi6-12/+12
2019-04-02clk: renesas: r8a774c0: Add Z2 clockSimon Horman1-0/+1
2019-04-02clk: renesas: r8a77990: Add Z2 clockTakeshi Kihara1-0/+1
2019-04-02clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parentsSimon Horman1-2/+2
2019-04-02clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman5-5/+3
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman6-20/+13
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara6-16/+28
2019-04-02clk: renesas: r9a06g032: Add missing PCI USB clockGareth Williams1-0/+1
2019-04-02clk: renesas: r7s9210: Always use readl()Geert Uytterhoeven1-1/+2
2019-03-18clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()Geert Uytterhoeven1-6/+6
2019-02-25clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLKFabrizio Castro1-1/+1
2019-02-22clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLKFabrizio Castro1-1/+1
2019-02-05clk: renesas: r8a774c0: Add TMU clockBiju Das1-0/+5
2019-02-05clk: renesas: r8a77980: Add RPC clocksSergei Shtylyov1-0/+8
2019-02-05clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov2-0/+105
2019-01-25clk: renesas: rcar-gen3: Add spinlockSergei Shtylyov1-0/+8
2019-01-25clk: renesas: rcar-gen3: Factor out cpg_reg_modify()Sergei Shtylyov1-18/+20
2019-01-24clk: renesas: r8a774c0: Correct parent clock of DUGeert Uytterhoeven1-2/+2
2019-01-21clk: renesas: r8a774a1: Add missing CANFD clockFabrizio Castro1-0/+2
2019-01-21clk: renesas: r8a774c0: Add missing CANFD clockFabrizio Castro1-0/+4
2018-12-15Merge branch 'clk-of' into clk-nextStephen Boyd1-1/+1
2018-12-15clk: Use of_node_name_eq for node name comparisonsRob Herring1-1/+1
2018-12-15Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd9-34/+58
2018-12-11clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd5-8/+8
2018-12-07Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd8-33/+46
2018-12-07clk: renesas: rcar-gen3: Add HS400 quirk for SD clockNiklas Söderlund1-7/+26
2018-12-07clk: renesas: rcar-gen3: Add documentation for SD clocksNiklas Söderlund1-5/+5
2018-12-07clk: renesas: rcar-gen3: Set state when registering SD clocksNiklas Söderlund1-12/+4
2018-12-04clk: renesas: r8a77995: Simplify PLL3 multiplier/dividerGeert Uytterhoeven1-2/+2
2018-12-04clk: renesas: r8a77995: Add missing CPEX clockGeert Uytterhoeven1-1/+2
2018-12-04clk: renesas: r8a77995: Remove non-existent SSP clocksGeert Uytterhoeven1-1/+0
2018-12-04clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocksGeert Uytterhoeven1-3/+0
2018-12-04clk: renesas: r8a77995: Correct parent clock of DUGeert Uytterhoeven1-2/+2
2018-12-04clk: renesas: r8a77990: Correct parent clock of DUTakeshi Kihara1-2/+2
2018-12-04clk: renesas: r8a77970: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a77965: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a7796: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a7795: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-12-04clk: renesas: r8a774a1: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-11-30clk: renesas: Mark rza2_cpg_clk_register staticStephen Boyd1-1/+1