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path: root/drivers/clk/tegra/clk-id.h
AgeCommit message (Expand)AuthorFilesLines
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni1-7/+0
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni1-2/+0
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni1-0/+1
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni1-0/+2
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding1-1/+1
2019-11-11clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding1-1/+1
2018-07-26clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver1-2/+0
2017-11-18Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-0/+1
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko1-0/+1
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver1-0/+6
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver1-1/+4
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver1-0/+6
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver1-0/+1
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding1-1/+0
2016-04-28clk: tegra: Add sor_safe clockThierry Reding1-0/+1
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding1-0/+1
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter1-0/+1
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein1-0/+7
2015-11-20clk: tegra: periph: Add new periph clks and muxes for Tegra210Rhyland Klein1-1/+67
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang1-2/+0
2014-05-23clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker1-0/+1
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker1-0/+4
2013-11-26clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver1-0/+22
2013-11-26clk: tegra: add header for common tegra clock IDsPeter De Schrijver1-0/+213