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master
Intel OpenBMC Linux kernel source tree (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
tegra
/
clk-tegra210.c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-05-12
clk: tegra: Add Tegra210 CSI TPG clock gate
Sowjanya Komatineni
1
-0
/
+7
2020-05-12
clk: tegra: Remove the old emc_mux clock for Tegra210
Joseph Lo
1
-19
/
+31
2020-05-12
clk: tegra: Export functions for EMC clock scaling
Joseph Lo
1
-0
/
+26
2020-05-12
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Joseph Lo
1
-0
/
+11
2020-03-25
clk: tegra: Use NULL for pointer initialization
Stephen Boyd
1
-1
/
+1
2020-03-12
clk: tegra: Remove audio clocks configuration from clock driver
Sowjanya Komatineni
1
-3
/
+2
2020-03-12
clk: tegra: Remove tegra_pmc_clk_init along with clk ids
Sowjanya Komatineni
1
-14
/
+3
2020-03-12
clk: tegra: Remove CLK_M_DIV fixed clocks
Sowjanya Komatineni
1
-4
/
+0
2020-03-12
clk: tegra: Add Tegra OSC to clock lookup
Sowjanya Komatineni
1
-0
/
+2
2020-03-12
clk: tegra: Add support for OSC_DIV fixed clocks
Sowjanya Komatineni
1
-0
/
+4
2019-11-11
clk: tegra: Fix build error without CONFIG_PM_SLEEP
YueHaibing
1
-0
/
+2
2019-11-11
clk: tegra: Add suspend and resume support on Tegra210
Sowjanya Komatineni
1
-4
/
+92
2019-11-11
clk: tegra: Use fence_udelay() during PLLU init
Sowjanya Komatineni
1
-4
/
+4
2019-11-11
clk: tegra: Reimplement SOR clocks on Tegra210
Thierry Reding
1
-16
/
+55
2019-11-11
clk: tegra: Rename sor0_lvds to sor0_out
Thierry Reding
1
-1
/
+1
2019-11-11
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
Thierry Reding
1
-1
/
+1
2019-07-17
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-8
/
+12
2019-06-28
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...
Linus Torvalds
1
-0
/
+2
2019-06-26
clk: tegra: Do not enable PLL_RE_VCO on Tegra210
Thierry Reding
1
-1
/
+0
2019-06-26
clk: tegra: Warn if an enabled PLL is in IDDQ
Thierry Reding
1
-1
/
+5
2019-06-26
clk: tegra: Do not warn unnecessarily
Thierry Reding
1
-2
/
+3
2019-06-26
clk: tegra210: fix PLLU and PLLU_OUT1
JC Kuo
1
-4
/
+4
2019-06-14
clk: tegra210: Fix default rates for HDA clocks
Jon Hunter
1
-0
/
+2
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Thomas Gleixner
1
-12
/
+1
2019-04-23
clk: core: replace clk_{readl,writel} with {readl,writel}
Jonas Gorski
1
-3
/
+3
2018-12-15
clk: tegra: Fix maximum audio sync clock for Tegra124/210
Jon Hunter
1
-1
/
+8
2018-10-17
clk: tegra210: Include size.h for compilation ease
Stephen Boyd
1
-0
/
+1
2018-10-17
clk: tegra: Fixes for MBIST work around
Joseph Lo
1
-3
/
+3
2018-07-26
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
Peter De-Schrijver
1
-2
/
+12
2018-05-18
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
Dmitry Osipenko
1
-1
/
+1
2018-03-12
clk: tegra: Mark HCLK, SCLK and EMC as critical
Dmitry Osipenko
1
-2
/
+1
2018-03-08
clk: tegra: MBIST work around for Tegra210
Peter De Schrijver
1
-2
/
+342
2018-03-08
clk: tegra: Add la clock for Tegra210
Peter De Schrijver
1
-0
/
+14
2017-11-01
clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()
Nicolin Chen
1
-2
/
+2
2017-10-19
clk: tegra: Fix sor1_out clock implementation
Thierry Reding
1
-0
/
+47
2017-08-24
clk: tegra: Fix Tegra210 PLLU initialization
Alex Frid
1
-2
/
+4
2017-08-24
clk: tegra: Correct Tegra210 UTMIPLL poweron delay
Alex Frid
1
-3
/
+3
2017-08-24
clk: tegra: Re-factor T210 PLLX registration
Alex Frid
1
-1
/
+1
2017-08-24
clk: tegra: don't warn for pll_d2 defaults unnecessarily
Peter De Schrijver
1
-2
/
+4
2017-08-24
clk: tegra: Fix T210 effective NDIV calculation
Alex Frid
1
-4
/
+5
2017-08-24
clk: tegra210: remove non-existing VFIR clock
Peter De Schrijver
1
-1
/
+0
2017-08-24
clk: tegra: disable SSC for PLL_D2
Peter De Schrijver
1
-1
/
+1
2017-04-04
clk: tegra: Don't reset PLL-CX if it is already enabled
Jon Hunter
1
-4
/
+4
2017-04-04
clk: tegra: Add missing Tegra210 clocks
Peter De Schrijver
1
-0
/
+7
2017-03-20
clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on
Peter De Schrijver
1
-0
/
+2
2017-03-20
clk: tegra: Add SATA seq input control
Peter De Schrijver
1
-0
/
+25
2017-03-20
clk: tegra: Add Tegra210 special resets
Peter De Schrijver
1
-0
/
+85
2017-03-20
clk: tegra: Rework pll_u
Peter De Schrijver
1
-23
/
+272
2017-03-20
clk: tegra: Handle UTMIPLL IDDQ
Peter De Schrijver
1
-0
/
+26
2017-03-20
clk: tegra: Add aclk
Peter De Schrijver
1
-0
/
+10
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